An Error Diagnosis Technique Combining BDD-based Approach and SAT-Solver and Its Application to Incremental Synthesis to Reduce Costs Needed for ECO's

2014 Fiscal Year Final Research Report

• Project/Area Number: 24500064
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Kobe University
• Principal Investigator: NUMA MASAHIRO 神戸大学, 工学(系)研究科(研究院), 教授 (60188787)
• Co-Investigator(Kenkyū-buntansha): KUROKI Nubutaka 神戸大学, 大学院工学研究科, 准教授 (90273763)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Keywords: 論理診断 / 論理再合成 / 設計変更 / SATソルバ / 設計誤り

Outline of Final Research Achievements

We have proposed and implemented an error diagnosis technique combining BDD-based functional approach and SAT-solver, which makes it possible to diagnose large scale circuits including a lot of logic design errors. In addition, we have applied it to an incremental synthesis system employing RECON (reconfigurable) cells to fix ECO’s (Engineering Change Orders) only by changing metal layer masks. The experimental results have shown that the proposed system is effective to reduce costs needed for ECO’s.

Free Research Field

ＶＬＳＩ設計技術