A study on helper-thread based runtime architectural state optimization methodology

2015 Fiscal Year Final Research Report

• Project/Area Number: 24680004
• Research Category: Grant-in-Aid for Young Scientists (A)
• Allocation Type: Partial Multi-year Fund
• Research Field: Computer system/Network
• Research Institution: The University of Tokyo (2013-2015); The University of Electro-Communications (2012)
• Principal Investigator: Kondo Masaaki 東京大学, 情報理工学(系)研究科, 准教授 (30376660)
• Project Period (FY): 2012-04-01 – 2016-03-31
• Keywords: 計算機アーキテクチャ / 並列・分散処理 / ハイパフォーマンスコンピューティング / メニーコア / マルチスレッド

Outline of Final Research Achievements

In this research, we developed a software-based runtime architectural state optimization methodology for manycore processors. We applied proposed method to the optimized control of cache line replacement with helper-threading in order to mitigate the cache contention. In this technique, the helper-thread optimizes and indicates the policy of date insertion position within a cache set with a page granularity. The hardware performs data replacement accordingly. Based on the cycle accurate simulation, it is revealed that the proposed method achieves about 11% performance improvement over the conventional hardware-based cache replacement.
As an extension of this research, we studied and analyzed code optimization for FPGA accelerators. We proposed some code modification strategies for achieving higher performance in OpenCL based FPGA accelerations and showed that they are effective in some cases.

Free Research Field

計算機アーキテクチャ