2013 Fiscal Year Final Research Report
Custom Instruction Generation for Multiprocessor SoCs
| Project/Area Number |
24700054
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Tokyo City University |
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Principal Investigator |
KENSHU Seto 東京都市大学, 工学部, 講師 (10420241)
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| Project Period (FY) |
2012-04-01 – 2014-03-31
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| Keywords | SoC / 高位合成 / ループパイプライン化 |
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| Research Abstract |
In the loop pipelining of high-level synthesis, the reduction of initiation intervals (IIs) is the key for high-performance. Traditional loop pipelining techniques, however, assume that the RAW dependences whose occurrences are unknown before execution always occur, resulting in increased IIs. In this research, we developed a technique that reduces IIs. In this technique, data written to memories in such dependences are also written to registers and the occurrences of the dependences are checked at runtime and the registers are accessed in case the dependences occur. We demonstrated that our technique reduces the numbers of execution cycles by 40% on average compared to the state-of-the-art loop pipelining technique.
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