2014 Fiscal Year Final Research Report
Development of a High-level Synthesis System for Path Delay Testability
| Project/Area Number |
24700056
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
|
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| Research Institution | Kure National College of Technology |
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Principal Investigator |
YOSHIKAWA Yuki 呉工業高等専門学校, 機械工学分野, 准教授 (50453212)
|
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| Project Period (FY) |
2012-04-01 – 2015-03-31
|
| Keywords | 遅延テスト容易性 / 高位合成 |
|---|
| Outline of Final Research Achievements |
The increase in speed and performance of LSIs result in the increase in defective chips. To reduce the yield loss of produced chips and the cost of them, development of high quality and low cost test techniques is important. This research project has proposed a method of design (or high level synthesis) for testability at behavioral level.
|
| Free Research Field |
LSI-CAD，高信頼設計
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