2015 Fiscal Year Final Research Report
Development of Wireless Jitter Testing System Using Inductive-Coupling Interface
Project/Area Number |
24760266
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Research Category |
Grant-in-Aid for Young Scientists (B)
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Allocation Type | Multi-year Fund |
Research Field |
Electron device/Electronic equipment
|
Research Institution | Nagoya University |
Principal Investigator |
Niitsu Kiichi 名古屋大学, 工学(系)研究科(研究院), 講師 (40584785)
|
Project Period (FY) |
2012-04-01 – 2016-03-31
|
Keywords | 半導体集積回路 / ジッタ / テスト容易化技術 / 低消費電力 / 低コスト / 高速化 / 集積回路設計 / アナログ集積回路 |
Outline of Final Research Achievements |
As an operational frequency of semiconductor integrated circuits (CMOS LSIs) is increasing rapidly, operational errors due to clock jitters become serious. In this research, wireless jitter testing system using low-power and low-cost inductive-coupling communication for reducing test cost was developed.
|
Free Research Field |
集積回路工学
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