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2017 Fiscal Year Annual Research Report

A Study on Building-Block Computing Systems using Inductive Coupling Interconnect

Research Project

Project/Area Number 25220002
Research InstitutionKeio University

Principal Investigator

天野 英晴  慶應義塾大学, 理工学部(矢上), 教授 (60175932)

Co-Investigator(Kenkyū-buntansha) 並木 美太郎  東京農工大学, 工学(系)研究科(研究院), 教授 (10208077)
中村 宏  東京大学, 大学院情報理工学系研究科, 教授 (20212102)
宇佐美 公良  芝浦工業大学, 工学部, 教授 (20365547)
近藤 正章  東京大学, 先端科学技術研究センター, その他 (30376660)
黒田 忠広  慶應義塾大学, 理工学部(矢上), 教授 (50327681)
Project Period (FY) 2013-05-31 – 2018-03-31
Keywordsコンピュータアーキテクチャ / System In Package / 性能、電力自動調整
Outline of Annual Research Achievements

ビルディングブロック型計算システムの構成例として、開発してIPを装備するチップを開発し、積層システムを構築した。7月にテープアウトしたチップは、ホストCPUでツインタワー構成に対応するGeyserTT、ニューラルネットワークアクセラレータSNACC、共有メモリシステムSMTT、データベース用アクセラレータKVSチップである。このうち、KVSチップはルネサスによるメモリ抜けのトラブルのため2月のテープアウトとなった。これに2016年度テープアウトして既に検証済のCCSOTB2を合わせて、5種類のチップを組み合わせることができる。個々のチップとしては、それぞれ所定の動作を行うことが確認できた。最後に、これらのチップを数種類のパターンで積層し、転送実験を行った。結果として転送には成功したが、一部の通信で問題が見つかった。

ビルディングブロック型計算システムを構成する上での性能の自動調整システムに関しては、プロトタイプが動作し、実際に与えた周波数に追従して、ボディバイアスを制御できることを確認した。また、2016年度に実装したCCSOTB2の性能と消費電力のバランスを細かいレベルで最適化する手法の研究を行い、実チップ上でその成果を確認した。
ビルディングブロック型のOSに関しては、柔軟なヘテロジーニアスシステムを構築するプログラミング環境を構築し、実チップとFPGAによる上でデモンストレーションを行った。
最終年度に当たり、ISOCC(International SOC Design Conference)でSpecial Sessionを行い、国際的に成果をまとめて発表した。また、国内向けには情報処理学会の全国大会にて2つのセッションを用いて発表を行うと共にデモンストレーションを行った。

Research Progress Status

29年度が最終年度であるため、記入しない。

Strategy for Future Research Activity

29年度が最終年度であるため、記入しない。

  • Research Products

    (34 results)

All 2018 2017 Other

All Journal Article (10 results) (of which Peer Reviewed: 10 results,  Open Access: 5 results) Presentation (22 results) (of which Int'l Joint Research: 22 results,  Invited: 6 results) Remarks (1 results) Funded Workshop (1 results)

  • [Journal Article] Body Bias Control for Renewable Energy Source with a High Inner Resistance2018

    • Author(s)
      Keita Azegami, Hayate Okuhara, Hideharu Amano
    • Journal Title

      IEEE Transactions on Multi-Scale Computing System

      Volume: Accepted Pages: 1-8

    • Peer Reviewed
  • [Journal Article] Optimization of Body Biasing for Variable Pipelined Coase Grained Reconfigurable Accelerators2018

    • Author(s)
      Takuya Kojima, Naoki Ando, Hayate Okuhara, Anh Vu Doan, Hideharu Amano
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E101-D, No.6 Pages: 1-13

    • Peer Reviewed / Open Access
  • [Journal Article] Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems2018

    • Author(s)
      Okuhara Hayate、Ben Ahmed Akram、Amano Hideharu
    • Journal Title

      IEEE Transactions on Circuits and Systems I: Regular Papers

      Volume: Accepted Pages: 1~14

    • DOI

      10.1109/TCSI.2018.2811504

    • Peer Reviewed
  • [Journal Article] Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization2018

    • Author(s)
      Hayate Okuhara, A.Ben Ahmed J.M.Kuehn, Hideharu Amano
    • Journal Title

      IEEE Transactions. on Very Large Scale Integrated Systems

      Volume: Accepted Pages: 1~14

    • DOI

      10.1109/TVLSI.2018.2812893

    • Peer Reviewed
  • [Journal Article] Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach2018

    • Author(s)
      Carlos Torres, Hayate Okuhara, Nobuyuki Yamasaki, Hideharu Amano
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E101-D, No.4 Pages: 1116-1130

    • Peer Reviewed / Open Access
  • [Journal Article] 低消費電力再構成可能アクセラレータの実装と評価2018

    • Author(s)
      増山滉一郎、藤田悠、奥原颯、天野英晴
    • Journal Title

      電子情報通信学会論文誌

      Volume: D100 Pages: 1‐14

    • Peer Reviewed / Open Access
  • [Journal Article] Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface2018

    • Author(s)
      Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano
    • Journal Title

      International Journal of Network and Computing

      Volume: Vol.8 No.1 Pages: 124‐139

    • Peer Reviewed / Open Access
  • [Journal Article] Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET2017

    • Author(s)
      Okuhara Hayate、Fujita Yu、Usami Kimiyoshi、Amano Hideharu
    • Journal Title

      IEEE Transaction on VLSI systems

      Volume: 25 Pages: 1578~1582

    • DOI

      10.1109/TVLSI.2016.2635675

    • Peer Reviewed
  • [Journal Article] Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers2017

    • Author(s)
      Yasudo Ryota、Matsutani Hiroki、Koibuchi Michihiro、Amano Hideharu、Nakamura Tadao
    • Journal Title

      IEEE Transactions on Computers

      Volume: 66 Pages: 702~716

    • DOI

      10.1109/TC.2016.2606597

    • Peer Reviewed
  • [Journal Article] Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator2017

    • Author(s)
      Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E100-D.No.12 Pages: 2828~2836

    • Peer Reviewed / Open Access
  • [Presentation] A Shared Memory Chips for Twin-Tower of Chips2018

    • Author(s)
      S.Terashima, T.Kojima, H.Okuhara, Y.Matsushita, N.Ando, M.Namiki, H.Amano
    • Organizer
      The 21th Workshop on Synthesis and System Integration Technologies
    • Int'l Joint Research
  • [Presentation] A building block computing system for AI applications2017

    • Author(s)
      Hideharu Amano
    • Organizer
      IEEE International Symposium on Embedded Multi-core System on Chips
    • Int'l Joint Research / Invited
  • [Presentation] Building Block multi-chip systems using inductive coupling through chip interface2017

    • Author(s)
      H.Amano, T.Kuroda, H.Nakamura, K.Usami, M.Kondo, H.Matsutani, M.Namiki
    • Organizer
      International SoC Design Conference
    • Int'l Joint Research / Invited
  • [Presentation] An Inductive Coupting Link for 3-D network-on-Chips2017

    • Author(s)
      J.Kadomoto, H.Amano, T.Kuroda
    • Organizer
      International SoC Design Conference
    • Int'l Joint Research / Invited
  • [Presentation] Scalable Deep Neural Network Accelerator Cores with Cubic Integration using Through Chip Interface2017

    • Author(s)
      R.Sakamoto, R.Takata, J.Ishi, M.Kondo, H.Nakamura, T.Ohkubo, T.Kojima, H.Amano
    • Organizer
      International SoC Design Conference
    • Int'l Joint Research / Invited
  • [Presentation] Building Clock Operating System for 3D Stacked Computer Systems with Inductive Coupling Interconnect2017

    • Author(s)
      S.Hamada, A.Koshiba, M.Namiki, H.Amano
    • Organizer
      International SoC Design Conference
    • Int'l Joint Research / Invited
  • [Presentation] Digital Embedded Memory Scheme using Voltage Scaling and Body Bias Separation for Low-Power System2017

    • Author(s)
      Y.Yoshida, K.Usami, H.Amano
    • Organizer
      International SoC Design Conference
    • Int'l Joint Research / Invited
  • [Presentation] Leveraging Asymmetric Body Bias Control for Low Power LSI Design2017

    • Author(s)
      H.Okuhara, A.B.Ahmed, J.M.Kuehn, H.Amano,
    • Organizer
      IEEE international symposium on Low Power and High Speed Chips
    • Int'l Joint Research
  • [Presentation] Body Bias Control for Renewable Energy Source with a High Inner Resistance2017

    • Author(s)
      K.Azegami, H.Okuhara, H.Amano,
    • Organizer
      IEEE international symposium on Low Power and High Speed Chips
    • Int'l Joint Research
  • [Presentation] Order/Radix Problem: Toward Low End-to-End Latency Interconnection Network2017

    • Author(s)
      R.Yasudo, M.Koibuchi, K.Nakano, H.Matsutani, H.Amano
    • Organizer
      48th Internaional Conference on Parallel Processing
    • Int'l Joint Research
  • [Presentation] Break Even Time Analysis Using Empirical Overhead Parameters for Embedded Systems on SOTB Technology2017

    • Author(s)
      C.Cortes, H.Amano
    • Organizer
      Design of Circuits and Integrated Systems Conference
    • Int'l Joint Research
  • [Presentation] XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs2017

    • Author(s)
      H.Nakahara, N.A.V.Doan, R.Yasudo, H.Amano
    • Organizer
      11th International Symposium on Networks-on-Chip
    • Int'l Joint Research
  • [Presentation] 3D layout of Spindergon, Flattened Butterfly and Dragonfly on a chip stack with inductive coupling through chip interface2017

    • Author(s)
      H.Nakahara, R.Yasudo, H.Matsutani, H.Amano, H.Koibuchi
    • Organizer
      The 14th International Symposium on Pervasive Systems, Algorithms and Networks
    • Int'l Joint Research
  • [Presentation] Switching Region Analysis for SOTB Technology2017

    • Author(s)
      C.Cortes, H.Amano
    • Organizer
      10th International Caribbean Conference on Devices Circuits and Systems
    • Int'l Joint Research
  • [Presentation] Basic Design of OS Scheduler for SOTB CPU "GC-SOTB" to reduce power consumption2017

    • Author(s)
      S.Hamada, A.Koshiba, M.Namiki
    • Organizer
      IEEE International Symposium on Embedded Multi-core System on Chips
    • Int'l Joint Research
  • [Presentation] Level Shifter Free Approach for Multi-VDD SOTB employing Adaptive Vt Modulation for pMOSFET2017

    • Author(s)
      K.Usami, K.Kogure, Y.Yoshida, R.Magasaki, H.Amano
    • Organizer
      IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
    • Int'l Joint Research
  • [Presentation] The design and implementation of Scalable Deep Neural Network Accelerator Cores2017

    • Author(s)
      R.Sakamoto, R.Takata, J.Ishii, M.Kondo, H.Nakamura, T.Ohkubo, T.Kojima, H.Amano
    • Organizer
      IEEE international symposium on Embedded Multicore/Many-core Systems-on Chip
    • Int'l Joint Research
  • [Presentation] Multi-Objective Optimization for Application Mapping and Body Bias Control on a CGRA2017

    • Author(s)
      N.A.V.Doan, Y.Matsushita, N.Ando, H.Okuhara, H.Amano
    • Organizer
      IEEE international symposium on Embedded Multicore/Many-core Systems-on Chip
    • Int'l Joint Research
  • [Presentation] Body bias optimization for variable pipelined CGRA2017

    • Author(s)
      T.Kojima, N.Ando, H.Okuhara, N.A.V.Doan, H.Amano
    • Organizer
      27th International Conference on Field Programmable Logic and Applications
    • Int'l Joint Research
  • [Presentation] A practical collision avoidance method for an inter-chip bus with wireless inductive through chip interface2017

    • Author(s)
      A.Nomura, J.Kadomoto, TKuroda, H.Amano
    • Organizer
      The 5th International Symposium on Computing and Networking
    • Int'l Joint Research
  • [Presentation] Glitch-aware variable pipeline optimization for GCRAs2017

    • Author(s)
      T.Kojima, N.Ando, H.Okuhara, H.Amano
    • Organizer
      International Conference on Reconfigurable Computing and FPGAs
    • Int'l Joint Research
  • [Presentation] HiRy: An advanced theory on design of deadlock-free adaptive routing for arbitrary toplogies2017

    • Author(s)
      R.Kawano, R.Yasudo, H.Matsutani, M.Koibuchi, H.Amano
    • Organizer
      IEEE 23rd International Conference on Parallel and Distributed Systems
    • Int'l Joint Research
  • [Remarks] A Study on Building Block Computing Systems

    • URL

      http;//www.am.ics.keio.ac.jp/kaken_s

  • [Funded Workshop] Special Session in International SoC Design Conference2017

URL: 

Published: 2018-12-17  

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