Source-level parallelization system for CPU/GPU combined heterogeneous architecture

2016 Fiscal Year Final Research Report

• Project/Area Number: 25330055
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Utsunomiya University
• Principal Investigator: Baba Takanobu 宇都宮大学, オプティクス教育研究センター, 教授 (70092616)
• Co-Investigator(Renkei-kenkyūsha): YOKOTA Takashi 宇都宮大学, 大学院工学研究科, 教授 (90334078) ; OHKAWA Takeshi 宇都宮大学, 大学院工学研究科, 助教 (80392596)
• Project Period (FY): 2013-04-01 – 2017-03-31
• Keywords: CPU/GPU混載プロセッサ / 実行プロファイリング / 自動並列化

Outline of Final Research Achievements

The increase of transistor count allows us to implement multicore-CPU and GPU combined heterogeneous architecture on a single chip. We have designed a source-level loop parallelization system framework for the heterogeneous architecture. Following the designed framework, we have developed a path and data-dependency profiling tool using Valgrind. By applying the system to benchmark programs, we have clarified the characteristics of each loop of the programs and showed that we can utilize the profiled results to determine the parallelizing scheme on heterogeneous architecture

Free Research Field

計算機システム