Development of Host-Based IPS Processor Using Delay Adjustment Method by Routing and Optimization of Detection Circuits

2016 Fiscal Year Final Research Report

• Project/Area Number: 25330149
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Information security
• Research Institution: Hirosaki University
• Principal Investigator: Sato Tomoaki 弘前大学, 総合情報処理センター, 准教授 (00336992)
• Project Period (FY): 2013-04-01 – 2017-03-31
• Keywords: IDS / IPS / FPGA / RTL / ウェーブパイプライン

Outline of Final Research Achievements

Unauthorized access and computer viruses cause problems with information leakage and tampering. Actually, a targeted attack made leakage of personal information in Japan Pension Service. In order to avoid unauthorized access and computer viruses, Intrusion Detection Systems (IDSs) or Intrusion Prevention Systems (IPSs) should be used. In this study, it is clarified that a fine-tuning method for wave-pipelining can be realized on reconfigurable hardware for the purpose of addressing these problems with a technical approach in mobile devices. In addition, the optimization of the detection circuit was realized by ASIC-FPGA co-design.

Free Research Field

計算機工学