Research on wireless transceiver-circuit complexity aware adaptive signal processing

2015 Fiscal Year Final Research Report

• Project/Area Number: 25420376
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Communication/Network engineering
• Research Institution: Kyushu University
• Principal Investigator: MUTA OSAMU 九州大学, 日本エジプト科学技術連携センター, 准教授 (80336065)
• Co-Investigator(Kenkyū-buntansha): KANEMOTO Daisuke 山梨大学, 総合研究部, 助教 (90603332)
• Co-Investigator(Renkei-kenkyūsha): FURUKAWA Hiroshi 九州大学, システム情報科学研究院, 教授 (60260725)
• Project Period (FY): 2013-04-01 – 2016-03-31
• Keywords: 無線通信 / MIMO / A/D変換器 / 適応信号処理

Outline of Final Research Achievements

In Multi-Input Multi-Output wireless communication systems, it is important to reduce hardware size and required power consumption at the transceiver circuits. In this research, we aim to develop efficient signal processing techniques to simplify the transceiver circuits. We proposed to use a low resolution analog-to-digital (A/D) converter (ADC) and related analog hardware designs to reduce the required analog hardware complexity at the receiver circuits. Then, to mitigate the nonlinearity of low-resolution ADC, we proposed nonlinearity mitigation techniques for low-resolution A/D conversion. In addition, we proposed a peak-power-aware linear-precoding scheme for MIMO-spatial multiplexing systems, where the precoder is designed to mitigate the peak output power at each antenna element. Furthermore, compressed sensing techniques are proposed for hardware-complexity reduced spectrum sensing. The effectiveness of the proposed techniques were clarified by computer simulation.

Free Research Field

無線通信