Efficient Subtract-Multiply Operation Circuit Design Using Selector Logics

2014 Fiscal Year Final Research Report

• Project/Area Number: 25540021
• Research Category: Grant-in-Aid for Challenging Exploratory Research
• Allocation Type: Multi-year Fund
• Research Field: Computer system
• Research Institution: Waseda University
• Principal Investigator: TOGAWA NOZOMU 早稲田大学, 理工学術院, 教授 (30298161)
• Project Period (FY): 2013-04-01 – 2015-03-31
• Keywords: セレクタ演算 / 差積演算 / 画像処理

Outline of Final Research Achievements

A subtract-multiply operation, (a-b)*c, is a basic and important operation in image processing but it requires much computation time since we first calculate t=(a-b) and, after that, we calculate t*c. In this report, we first show that the subtract-multiply operation can be effectively implemented by “selectors.” After that, we pick up bi-linear interpolation and apply the selector-logics to it. Selector logics can reduce the carry-propagations and then we can realize area-efficient and fast dedicated circuits. We have implemented our proposed bi-linear interpolation circuit in several ways and evaluated each of them.

Free Research Field

集積システム設計