Epitaxial growth of Ge with low defect density on ultrathin Si layers

2015 Fiscal Year Final Research Report

• Project/Area Number: 25630121
• Research Category: Grant-in-Aid for Challenging Exploratory Research
• Allocation Type: Multi-year Fund
• Research Field: Electronic materials/Electric materials
• Research Institution: The University of Tokyo
• Principal Investigator: Ishikawa Yasuhiko 東京大学, 工学(系)研究科(研究院), 准教授 (60303541)
• Project Period (FY): 2013-04-01 – 2016-03-31
• Keywords: エピタキシャル / 結晶成長 / 電子・電気材料 / 格子欠陥 / 半導体物性

Outline of Final Research Achievements

In order to realize epitaxial growth of Ge with a low defect density on SOI (Si-on-Insulator) wafers, Ge epitaxial growth was performed on SOI wafers having ultrathin and patterned top Si layers. A lattice relaxation took place, accompanying a surface roughening and a SiGe alloying, prior to the generation of dislocations in ultrathin Si patterns. Further investigations such as the growth at a reduced temperature are necessary to maintain the layered structures and realize Ge layers with a low dislocation density.

Free Research Field

半導体工学