2015 Fiscal Year Final Research Report
Power Recovery Technique in Integrated Circuit for Wireless Communication
| Project/Area Number |
25630161
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Communication/Network engineering
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| Research Institution | Osaka University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
SHIOMI Hidehisa 大阪大学, 大学院基礎工学研究科, 助教 (00324822)
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| Project Period (FY) |
2013-04-01 – 2016-03-31
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| Keywords | 非線形増幅器 / 周波数利用効率 / 線形化 / アウトフェーズ / 集積回路 / ミリ波サブミリ波通信 / 電力回収 / 電力再利用 |
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| Outline of Final Research Achievements |
Many researchers are now working to reduce power consumption of portable wireless terminals with their high-performance. In digital circuits, the process miniaturization is the major driving force to achieve the low-power consumption. However, we cannot expect to improve the analog circuits by using same method. Conventionally, nonlinear amplifiers with high efficiency are utilized for this purpose. On the other hand, this method is not available for the multilevel modulation for the reason of large signal fluctuation. Here, we propose a newly circuit architecture named out-phase architecture in which a lot of analog circuits are replaced by digital circuits to reduce the power consumption. The proposed architecture can realize many convenient functions such as highly linear power amplifiers, highly linear frequency multipliers and so on. Furthermore, we try to take the power recovery circuits into the proposed circuits to collect the unwanted power and demonstrate their usefulness.
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| Free Research Field |
電気電子工学
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