A Study of Novel Computer Architecture for High-efficient Processor Cores and its Multicore Structure

2016 Fiscal Year Final Research Report

• Project/Area Number: 25730028
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Computer system
• Research Institution: The University of Tokyo (2015-2016); The University of Electro-Communications (2013-2014)
• Principal Investigator: Hidetsugu Irie 東京大学, 大学院情報理工学系研究科, 准教授 (50422407)
• Project Period (FY): 2013-04-01 – 2017-03-31
• Keywords: コンピュータ・アーキテクチャ / プロセッサ / コンパイラ / HDL / マイクロアーキテクチャ / キャッシュ・メモリ / 命令レベル並列実行

Outline of Final Research Achievements

In this research, we developed a novel computer architecture which enables sustainable improvement of the computing performance. By improving the technology in that CPU automatically optimizes the execution at runtime, this study complements the technology that optimizes the execution based on the given instructions by the programmers such as many-core or SIMD technologies. In the first year we proposed an original instruction set which is characterized by eliminating register overwrites, and in the second year we clarified that this feature resolves the weak point of conventional CPUs. In the third year, dedicated compiler is developed, and in the final year our architecture is strengthened by novel HW/SW optimizing technology. These results reveal that the execution efficiency of our architecture is expected to be several times higher than conventional, and this research has shifted to the next stage such as system design and extension to artificial intelligence correspondence.

Free Research Field

コンピュータ・システム