Configuration Method of Dependable Network-on-Chip Based on Partial Reconfiguration

2014 Fiscal Year Final Research Report

• Project/Area Number: 25730030
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Computer system
• Research Institution: Yamaguchi University
• Principal Investigator: FUKUSHI MASARU 山口大学, 理工学研究科, 准教授 (50345659)
• Project Period (FY): 2013-04-01 – 2015-03-31
• Keywords: ネットワークオンチップ / 高信頼アーキテクチャ / ネットワーク再構成 / 耐故障ルーティング / 部分再構成

Outline of Final Research Achievements

Toward the realization of large-scale on-chip parallel systems, this research project studied the configuration method of dependable Network-on-Chip (NoC) to tolerate defects and faults in the systems. Introducing the concept of partial reconfiguration, we developed a novel approach which combines two different fault-tolerance technologies, network reconfiguration and fault-tolerant routing. This approach has shown to reduce the significant degradation of NoC size and communication performance which was the critical problem in the previous methods, and enable the customization of NoC to meet the performance requirements imposed by the target applications.

Free Research Field

並列分散システム