Maximize the Efficiency of LSI DesignFlow with Advanced LSI Test Method

2015 Fiscal Year Final Research Report

• Project/Area Number: 25730031
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Computer system
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: Miyase Kohei 九州工業大学, 大学院情報工学研究院, 助教 (30452824)
• Project Period (FY): 2013-04-01 – 2016-03-31
• Keywords: VLSI設計技術

Outline of Final Research Achievements

In this work, we proposed a method to extract important areas in terms of controlling power consuming of LSI testing. Also, we proposed a method to generate test patterns for the extracted areas. The results of above methods can be integrated, and then they can contribute to increase the efficiency of the LSI design flow. The results of extraction of areas can be used for power network synthesis and power-aware test pattern generation. The proposed test pattern generation can contribute to increase effectiveness of detection, reliability, and quality of LSI. We have published this work in two international symposiums, one international workshop, and one Japanese workshop.

Free Research Field

LSIテスト