HPC Interconnects toward Ultra-low-delay Era

2014 Fiscal Year Final Research Report

• Project/Area Number: 25730068
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Information network
• Research Institution: National Institute of Informatics
• Principal Investigator: FUJIWARA Ikki 国立情報学研究所, アーキテクチャ科学研究系, 特任准教授 (90648023)
• Project Period (FY): 2013-04-01 – 2015-03-31
• Keywords: ネットワーク

Outline of Final Research Achievements

This research clarified how to design an ultra-low-latency network that connects tens of thousands of computers within a large-scale parallel computing systems such as next-generation supercomputers. We developed a sophisticated method to design a network topology and a routing algorithm that minimizes the end-to-end latency. Existng design method for supercomputer networks did not take a cable delay into account, of which our proposed method explicitly take care. When comparing to a former state-of-the-art network design, our design achieves merely 6% higher communication latency while consuming 65% smaller amount of cable. As such, our proposed design method provides a desirable trade-off between cost and performance.

Free Research Field

ハイパフォーマンスコンピューティング