Design space exploration of highly energy efficient processors by fine-grain 3-D IC stacking technologies

2016 Fiscal Year Final Research Report

• Project/Area Number: 26330058
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Yamagata University
• Principal Investigator: Tada Jubee 山形大学, 大学院理工学研究科, 助教 (30361273)
• Project Period (FY): 2014-04-01 – 2017-03-31
• Keywords: 計算機アーキテクチャ / 三次元積層技術 / 集積回路設計

Outline of Final Research Achievements

The purpose of this study is to realize a highly energy efficient processor by using a fine-grain 3-D IC stacking technology. At first, this study aimed to improve components of the processor by the 3-D IC stacking. As a result, it has been shown that the fine-grain partitioning of the components could improve the performance and the power consumption of the arithmetic unit. As compared to the 2-D implementation, the 3-D stacked arithmetic unit improved the performance up to 20%, and the power consumption up to 10%. Next, in order to improve the energy efficient of the computing node which has several floating-point units, the fine-grain circuit partitioning method was considered and the design space was explored. As a result, As compared to the 2-D implementation, the 3-D stacked computing node achieved an 8% performance improvement and an 18% power consumption reduction in maximum.

Free Research Field

計算機アーキテクチャ