VLSI Implementation of Generic Hardware for Machine Learning

2016 Fiscal Year Final Research Report

• Project/Area Number: 26330065
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Osaka University
• Principal Investigator: Onoye Takao 大阪大学, 情報科学研究科, 教授 (60252590)
• Project Period (FY): 2014-04-01 – 2017-03-31
• Keywords: 機械学習 / VLSI / アーキテクチャ

Outline of Final Research Achievements

In this research, design of generic hardware for high speed classification in machine learning is proposed with providing flexible adaptability of its hardware organization. Specifically, a Support Vector Machine, which has inherent versatility for applications is accelerated by soft-cascade processing while maintaining its classification capability. Dimension of feature vectors and bit precision in calculation can be controlled without re-designing hardware. VLSI implementation is coordinated with the use of FPGA and 45nm technology to confirm the ability of adaptive reconfiguration. The designed FPGA and 45nm circuit attain 79VGA frames/7HD frames processing and 361VGA frames/35HD frames processing per second, respectively.

Free Research Field

応用集積システム