Timing Error Prediction for Variation-Resilient LSI Designs

2016 Fiscal Year Final Research Report

• Project/Area Number: 26330073
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Waseda University
• Principal Investigator: SHI YOUHUA 早稲田大学, 理工学術院, 准教授 (70409655)
• Project Period (FY): 2014-04-01 – 2017-03-31
• Keywords: 高信頼化 / ディペンダブルコンピューティング / LSI設計 / 製造ばらつき / ソフトエラー

Outline of Final Research Achievements

With technology scaling, process, voltage, and temperature (PVT) variations and soft errors pose great challenges on integrated circuit designs. In this project, we conduct researches on in-situ error prediction for dependable low energy LSI designs, which is achieved by introducing the concept of prediction into LSI designs as a solution to the reliability problems of state-of-the-art integrated circuits. At first, a predication-based timing monitoring method called suspicious timing error prediction (STEP) was proposed for variation-resilient LSI designs. And then low power soft error tolerant latch designs have been developed to deal with the soft error problem. Finally, an in-situ prediction-based AVS method was proposed for energy minimization, which has been implemented and verified on a real large processor design.

Free Research Field

情報学