A Reduction Technique for Temporal-Spatial Vth Variations and Leakage in a Coordinated Manner for SRAM-ReRAM Stacked Memories

2016 Fiscal Year Final Research Report

• Project/Area Number: 26420326
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Fukuoka Institute of Technology
• Principal Investigator: Yamauchi Hiroyuki 福岡工業大学, 情報工学部, 教授 (70425239)
• Project Period (FY): 2014-04-01 – 2017-03-31
• Keywords: SRAM / ReRAM / 時空間ランダムばらつき / デコンボリューション

Outline of Final Research Achievements

This study is to address the two critical issues facing the area and power-supply voltage Vdd scaling of the VLSI in a coordinated manner: increasing of (1) spatial and temporal threshold-voltage variations (σVt_RTN) and (2) sub-threshold leakage. To quantitatively evaluate the effectiveness of the proposed control operations for reducing the probability of multiple electron trapping status, statistical analysis tools with blind deconvolution ringing behavior avoidance techniques were developed. It is found that the key to avoid the ringing behavior is to adjust the phase of the distribution tails between the two blind deconvolution objects. The ringing behavior avoidance techniques are evaluated under wide ranges of slope of the distribution tails.

Free Research Field

VLSI