III-V semiconductor-based spin transistors: fabrication technique

2015 Fiscal Year Final Research Report

• Project/Area Number: 26630150
• Research Category: Grant-in-Aid for Challenging Exploratory Research
• Allocation Type: Multi-year Fund
• Research Field: Electron device/Electronic equipment
• Research Institution: The University of Tokyo
• Principal Investigator: Nakane Ryohso 東京大学, 工学(系)研究科(研究院), 准教授 (50422332)
• Project Period (FY): 2014-04-01 – 2016-03-31
• Keywords: スピントロニクス / 強磁性薄膜 / 電子材料 / 半導体デバイス

Outline of Final Research Achievements

The purpose of this study is to fabricate ferromagnetic electrodes/III-V semiconductor structure which is applicable to the source and drain contacts of spin metal-oxide-semiconductor field-effect transistors fabricated with the self-aligned process. Fabrication of ferromagnetic alloys was performed by annealing of metal/semiconductor structures, and the resulting alloys were analyzed.
In the case of Mn/InGaAs structures, ferromagnetic alloys were not obtained for all the fabrication conditions. In the case of Mn/InP structures, single-phase ferromagnetic alloy MnP was obtained for some annealing conditions, which were characterized by X-ray reflective diffraction and magnetic hysteresis. However, the MnP films do not have flat surfaces and there was a void in the vicinity of the MnP/InP interface in the lateral direction. Thus, these issues should be overcome by optimizing fabrication process.

Free Research Field

スピントロニクス