Design of Ultra-Low Power IP-Packet-Processing LSI Based on Probabilistic Computing

2017 Fiscal Year Final Research Report

• Project/Area Number: 26700003
• Research Category: Grant-in-Aid for Young Scientists (A)
• Allocation Type: Partial Multi-year Fund
• Research Field: Computer system
• Research Institution: Tohoku University
• Principal Investigator: Onizawa Naoya 東北大学, 学際科学フロンティア研究所, 助教 (90551557)
• Project Period (FY): 2014-04-01 – 2018-03-31
• Keywords: 連想メモリ / 確率的演算 / Internet of Things / ニューラルネットワーク / 検索ハードウェア

Outline of Final Research Achievements

Recently, internet traffic has been expected to be rapidly increased. IP routers used as repeaters need to handle enormous packets while achieving high-speed and ultra-low power processing.
In this research, a probabilistic-computing based partial search algorithm has been presented for IP packet processing. Compared with a conventional method that requires a brute-force search, the proposed method achieves the comparable search capability using the partial searching, leading to an order-of-magnitude reduction in power dissipation.
As a result, this research results are summarized in 17 journals including well-known IEEE journals in the field and 38 conference presentations.

Free Research Field

計算機システム