Arbitrary data-width cache memory architecture in multi-FPGA systems

2016 Fiscal Year Final Research Report

• Project/Area Number: 26730026
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Computer system
• Research Institution: University of Tsukuba
• Principal Investigator: Kanazawa Kenji 筑波大学, システム情報系, 助教 (40707874)
• Project Period (FY): 2014-04-01 – 2017-03-31
• Keywords: FPGA / キャッシュ

Outline of Final Research Achievements

We studied arbitrary data-width cache memory architecture in multi-FPGA systems which consist of multiple FPGAs and off-chip DRAMs. Using the number of FPGAs and topologies of the interconnect of the FPGAs as parameters, we evaluated its performance on several applications including the satisfiability (SAT), the maximum satisfiability (MaxSAT), the partial-MaxSAT, calculation of convex hulls and the quadratic assignment problems, and then made it clear which configuration achieved the maximum performance for each application.

Free Research Field

Reconfgurable computing