2015 Fiscal Year Final Research Report
Placement and Routing Algorithm for Ultra Low Power FPGA with Programmable Threshold Voltage
| Project/Area Number |
26730030
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | Kanazawa Institute of Technology |
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Principal Investigator |
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| Project Period (FY) |
2014-04-01 – 2016-03-31
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| Keywords | FPGA / 低消費電力化 / スラック |
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| Outline of Final Research Achievements |
One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA.
This study aims to further reduce the power consumption of the Flex Power FPGA. This study is to improve the placement and routing algorithm of the design tool . Results of preliminary evaluation , correlation has been assumed at the time of the proposed could not be found . However from the preliminary evaluation , by giving priority to each element of FPGAs , the new proposed algorithm was able to significantly improve the power consumption and execution time than previous threshold voltage assignment algorithm.
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| Free Research Field |
リコンフィギャラブルシステム
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