Development of high quality semipolar-GaN substrates by HVPE with improved source-utilization efficiency

2016 Fiscal Year Final Research Report

• Project/Area Number: 26790044
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Crystal engineering
• Research Institution: Toyohashi University of Technology
• Principal Investigator: YAMANE KEISUKE 豊橋技術科学大学, 工学(系)研究科(研究院), 助教 (80610815)
• Project Period (FY): 2014-04-01 – 2017-03-31
• Keywords: ＧａＮ基板 / 結晶欠陥 / 非極性面 / 反り

Outline of Final Research Achievements

We developed high-quality GaN wafers for efficient white LEDs. From systematic investigations for various semipolar planes of GaN, it was revealed that {20-2-1} plane indicated high growth rate (efficient utilization efficiency of Ga source) and low dislocation density. In addition, mechanism of wafer bow was clarified from both experimental and theoretical aspects. Based on obtained results, a new growth method to suppress the wafer bow is also developed. For the purpose of reduction of crystalline defects, the combination of facet growth and surface flattening were effective. At the final stage of the project, we achieved the overall dislocation density of 10E5 cm-2.

Free Research Field

結晶工学　半導体工学