Minimization of variation and noise of electrical characteristics of MOS transistors due to atomically flat gate insulator film/Si interface

2015 Fiscal Year Final Research Report

• Project/Area Number: 26820121
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Electron device/Electronic equipment
• Research Institution: Tohoku University
• Principal Investigator: Kuroda Rihito 東北大学, 工学(系)研究科(研究院), 准教授 (40581294)
• Project Period (FY): 2014-04-01 – 2016-03-31
• Keywords: 電子デバイス・電子機器 / 電子デバイス・集積回路 / しきい値ばらつき / ランダム・テレグラフ・ノイズ / 原子レベル平坦化

Outline of Final Research Achievements

Atomically flattening technology of Si surface was introduced to a 0.22μm LSI manufacturing technology with shallow trench isolation process, and the atomic flatness of gate insulator/Si interface of MOS transistors was successfully obtained on the whole surface of 200mm diameter Si wafers. Based on the electrical characteristics measurement of over a million transistors, a reduction of threshold voltage variation as well as the one order of magnitude reduction of occurrence probability of random telegraph noise were confirmed and its reduction mechanism was clarified.

Free Research Field

半導体デバイス