2015 Fiscal Year Research-status Report
Self-learnable Analog-Digital-Mixed VLSI Processors for Smart Human-Computer-Interaction
| Project/Area Number |
26870227
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| Research Institution | Japan Advanced Institute of Science and Technology |
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Principal Investigator |
ZHANG Renyuan 北陸先端科学技術大学院大学, 情報科学研究科, 助教 (00709131)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Keywords | Analog-Digital-Mixed / Hybrid computing / Multi-Valued Logic / HCI / Neuron-MOS / FPGA |
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| Outline of Annual Research Achievements |
We developed several types of computational processors, memory systems, and relevant circuits for human-computer-interaction (HCI) data. From our previous investigations, the HCI data processing is different from general purpose calculations: it should be fast and efficient, but inaccuracy tolerant. Thus, we built many multi-valued-logic processors in the fashion of FPGA.
During the previous year of this project, we proposed several 4-valued logic (quaternary) FPGAs. However, it is still not satisfying since quaternary data is too inaccurate for HCI processing. Thus, we developed 16-valued logic (Hexadecimal) circuitries to compact the interconnections in further. We successfully verified the behavior of Hexadecimal processors, which greatly reduce the number of devices and interconnections.
In HCI processing, image recognition for instance, Gaussian function is very important. Thus, we designed the hexadecimal FPGAs to implement functions such as Gaussian. From experiments, the designed hexadecimal FPGA carried out all the expected functions reliably; and greatly reduce interconnections (from four to one), which allows us to implement fully parallel computing for HCI tasks.
Another progress lies on the development of analog and hexadecimal memories. The data for HCI is usually sensed from human or nature in the form of analog values. We developed several types of analog and hexadecimal SRAM with benefits of interconnections, power, and number of devices.
We disclosed our new progresses on some international journals and conferences with acknowledgement for this project.
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| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
The research progress was made smoothly as we expected, since we have developed necessary hardware parts in general. The reasons are given as follows:
1. From previous works, it has been proved it is feasible to compute in silicon by multi-valued logic (MVL) circuits such as quaternary. 2. We have successfully expanded quaternary to hexadecimal. As reported in some relevant works, hexadecimal computing is practical in some HCI processing tasks. 3. We solved the memory problems for either hexadecimal or analog towards to our specific applications. 4. From all of our experiments, the proposed hexadecimal processors achieved acceptable reliability and robustness to process and temperature variations. 5. All of our proposed circuits achieved obvious benefits on interconnections, power consumption, and number of devices, which are superior to previous/existing works in this research field. 6. We disclosed our progresses as some technical papers. The scientific societies basically agree with our explorations. On the other hand, we received some comments to improve our works in the future.
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| Strategy for Future Research Activity |
The efforts in two domains will be made in the coming year: hardware improvements and real-world applications.
Hardware improvements: as some researchers commented, our hexadecimal circuits and systems suffer from noise problems due to a small margin. So far, we proposed to insert hexadecimal buffers on the long data paths for cutting the noise propagation. In further, we are trying to develop self-calibration technologies in our hexadecimal circuits. We also plan to improve the hexadecimal SRAM by reducing the number of devices.
Applications/algorithms: for the target of HCI tasks, we are going to investigate if hexadecimal computing (4 bits) is sufficient for our specific applications such as image classification. Thus, we will directly implement some simple classification algorithms by software efforts, but use only 4-bit data and calculation accuracy. By adapting those algorithms, we want to design a small hexadecimal system for proof-of-concept. A reasonable application is two-dimensional pattern recognition.
As a concluding year, we hope to report our research progresses in the form of high quality technical papers.
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| Causes of Carryover |
We almost made full use of the budget exactly, just with a slight remain (1% of plan). This is due the price and currency fluctuation of journal publication charge and traveling cost.
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| Expenditure Plan for Carryover Budget |
The remain of previous year will be accumulate into the coming year to support paper publication charge.
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