2016 Fiscal Year Research-status Report
Self-learnable Analog-Digital-Mixed VLSI Processors for Smart Human-Computer-Interaction
| Project/Area Number |
26870227
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| Research Institution | Japan Advanced Institute of Science and Technology |
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Principal Investigator |
ZHANG Renyuan 北陸先端科学技術大学院大学, 先端科学技術研究科, 助教 (00709131)
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| Project Period (FY) |
2014-04-01 – 2018-03-31
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| Keywords | Analog-Digital-Mixed / Hybrid computing / Multi-Valued Logic / HCI / Neuron-MOS / FPGA |
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| Outline of Annual Research Achievements |
During the third year of this project, we expended the processing logic from quaternary to hexadecimal including the calculator, memory, and hexadecimal-to-binary converters as interfaces. Especially for the hexadecimal memory strategies, we developed two types of memory circuits: analog random access memory and hexadecimal flip-flop (which we call “H-FF”). In addition, the reliability of hexadecimal processors and memories was investigated. Through these efforts, we built the robust Gaussian Function calculator and its memory structures, which is widely applied for pattern recognitions in HCI systems.
In order to adapt our proposed hexadecimal computing processor in the general purpose HCI systems, we built a flash hexadecimal-to-binary (and also binary-to-hexadecimal) converter without static power consumption. Thus, all of our designed processors offer two types of input/output modes.
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| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
The purpose of this project is to explore the analog-digital-hybrid computational core for HCI calculations. Since we developed entire processing and memory structures of hexadecimal logic, the progress was made smoothly. From previous experiences, four-bit is sufficient for many specific image processing tasks. Thus, the hexadecimal logic is considered as a reasonable solution for our future efforts on HCI circuits and systems. On the other hand, we received some comments from relevant societies doubting the reliability and generality of hexadecimal.We spent much effort on investigating the circuit robustness and designing interface circuits. As a result, we obtained the acceptable robustness and a high-speed and low-power interface between our processors and general systems on chip.
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| Strategy for Future Research Activity |
The coming year is an extent year of this project. We are planning to make a demonstration on-chip learning processor by using the proposed analog-digital-hybrid core; and present the result as a technique paper for concluding this project.
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| Causes of Carryover |
According to the comments from some societies, the reliability of hexadecimal processors should be investigated. We made additional experiments and delay the plan of paper submission. The new paper submission is expected to cover the reliability analysis and an additional hexadecimal-to-binary interface circuit.
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| Expenditure Plan for Carryover Budget |
We have summarized the relevant improvement of our proposed circuits and submitted a technique paper. The remains of budget will be used to cover the publication cost of that paper.
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