1985 Fiscal Year Final Research Report Summary
LSI-Oriented Digital Signal Processing System Based on Residue Arithemtic Circuits and Its Comprehensive Evaluation
| Project/Area Number |
59850066
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| Research Category |
Grant-in-Aid for Developmental Scientific Research
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| Allocation Type | Single-year Grants |
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| Research Field |
計測・制御工学
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| Research Institution | Tohoku University |
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Principal Investigator |
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| Project Period (FY) |
1984 – 1985
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| Keywords | residue number system / digital signal processor / multiplier / LSI / pipelining |
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| Research Abstract |
The increasing demands of speed and performance in modern signal processing clearly point to the need for tremendous computation capability. On the other hand, low-cost, high-density, fast VLSI devices make such super-computing increasingly practical interms of volume, speed and cost. In almost all arithmetic chips, the conveitional binary number system in used. Another interesting approach for realizing high-performance VLSI arithmetic circuits can be found in the use of the residue number representation.
In this research, a new residue number multiplication scheme is proposed based on the following property: Every finite field has a primitive root whose powers generate all the field elements except zero. Using this scheme, a high-performance, pulse-train multiplier can be constructed with the same amount of hardware as the residue number adder. This feature cannot be seen in conventional arithmetic circuits, so that the proposed multiplier is very superior from the viewpoints of both compactness and speed.
The flexibility of the multiplier is suitable for implementing an RNS based high-order FIR digital signal processing using a programmable low-order section. The computations proceed in a pipelining manner with no idle state in each arithmetic component, so that the highest sampling rate can be obtained. Experimental results confirm the feasibility of the pulse-train residue based RNS arithmetic circuits in digital signal processing.
Finally, it is shown that a design method for LSI-oriented signal processor is discussed. The performance and the chip area are evaluated using circuit analysis program SPICE and hand layout. As a result, it is established that the proposed processor is very superior to the conventional implementations because of the regularity, simplicity of the residue arithmetic circuits suitable for pipelining operations.
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