| Co-Investigator(Kenkyū-buntansha) |
NAKAYA Itsuko Dept. of Information Science, Faculty of Engineering, Kyoto University, 工学部情報工学科, 教務職員 (40115902)
KUNIEDA Yoshitoshi Dept. of Information Science, Faculty of Engineering, Kyoto University, 工学部情報工学科, 助手 (90153311)
OKUBO Eiji Dept. of Information Science, Faculty of Engineering, Kyoto University, 工学部情報工学科, 講師 (60127058)
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| Research Abstract |
The compiler, which has resulted from this research project, is made of five phases. (1) Phase 1 : syntax and semantics analysis, (2) Phase 2 : pre-processing for vectorization, (3) Phase 3 : vectorizing and parallelizing, (4) Phase 4 : post-processing for vectorization, (5) Phase 5 : object-code generation. In phase 1, this compiler converts a given source program to specially designed intermediate codes. The source language is a subset of PASCAL 8000. In phase 2, the compiler optimizes the code and detects aliases. The optimizing techniques are chosen in such a way that they can : (A) increase vectorizable parts and (B) reduce costs of analyses. The phase 3 is made up from those modules given to : data-flow-analysis, control-flow analysis, dominator analysis, loop detection, control-dopendence analysis, data-dependence analysis, re-ordering of the intermediate codes, conversion of control structures, vectorization and parallelization. In phase 4, the compiler mainly optimizes scalar loops, and in phase 5, it generates machine codes. The target machine of this compiler is HITAC S-810, whose machine language allows us to express parallelism with ease. The size of the first version of this compiler is about 32,000 lines. The algorithm implemented in this compiler can vectorize the whole nested loops which may include If-then-else structures and/or exits from them, thus giving a breakthrough to the conventional vectorization technique.
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