| Research Abstract |
The integration density of VLSI is increasing year by year with the requirement of high speed and high density. It should be noted that, even at present time, the integration density of logic-VLSI which requires the large power dissipation for high speed operation is limited by the thermal capability of the chip. Although cryoelectronics based on the Josephson logic circuit is one of the high-speed and high-density LSI's, We notice that cold electronics based on Si VLSI technology is the most promising candidate which can break through the present limitation of VLSI. This research project was carried out under the following subjects :
1. To develop a new package concept in which the thermal capability is one or two order larger than that of the conventional packages.
2. To develop a new design principle of low-temperature operated high-speed Si MOSFET, and to fabricate basic MOS devices for low-temperature operation. In this research project, we carried out detailed work on cold electron
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ics for four years (1987-1990) and obtained the following results :
1. We proposed "a microchannel fin package" utilizing an AIN passivation layer as the heat spreader inside the chip and a microchannel fin as the efficient heat removal method from the chip. Thermal capability of the new package was evaluated using our simulator of dynamic thermal analysis in two/three dimensions. When the water-cooled microchannel fin is used, the dissipation power in a VLSI chip is quite allowable as high as 1.5kW/cm^2. More than 500k-gate ECL circuits with 3mW per gate are sufficiently integrated on a 1-cm^2 chip. When a compressive-air-cooled microchannel fined, the dissipation power is allowable as high as 30W/cm^2. The thermal capability of the microchannel fin package is one or two order larger than that of the conventional package.
2. We proposed a new scaling theory, "a temperature-scaling theory", relating to the operation temperature. Using our device simulator in two/three dimensions, we found that current-voltage characteristics were scaled down in proportion to the operation temperature, while the mobile-carrier distribution was kept constant. According to the temperature scaling theory, the optimum supply voltage for 0.1mum MOSFET is 1-1.5V and the gate delay times is estimated to be 1.6psec. Furthermore, we fabricated a LaB_6-gate MOSFET for freeze-out-free depletion-type MOSFET of high-speed E/D MOSLSI at low temperature. The work function of LaB_6 thin film was determined to be 3.5eV from C-V curves of LaB_6/SiO_2/p-Si MIS structure. The LaB_6-gate MOSFET fabricated using the self-align technique exhibited FET characteristics. Less
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