1988 Fiscal Year Final Research Report Summary
A VLSI-ORIENTED INTERCONNECTION NETWORK HAVING SELF-SIMILARITY
| Project/Area Number |
62550262
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | TOYOHASHI UNIVERSITY OF TECHNOLOGY, FACULTY OF ENGINEERING |
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Principal Investigator |
TATSUMI Shoji TOYOHASHI UNIVERSITY OF TECHNOLOGY, FACULTY OF ENGNEERING, ASSIST PROF., 工学部, 助教授 (80124733)
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| Project Period (FY) |
1987 – 1988
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| Keywords | Interconection Network / Systolic Array / Global Communication / Grid-connected Processor Array / Dynamic Programing / Orthogonal Projection Method / Separable Global Bus / 面積時間積 |
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| Research Abstract |
This research discusses the computation power and the design method of array-structured architectures which are regular style and suitable for VLSI implementation from the viewpoint of algorithm theory. The results are as follows. 1. A systematic design method for systolic algorithms is proposed. The proposed method is based on the idea that the transformation of a sequential algorithm to a parallel algorithm with the systolic property corresponds to the mapping of the structure (in the Euclidian space R^3) standing for a triple nested loop program as a specification of a given problem onto the proper hyperplane using orthogonal projection. 2. We discuss the design and analysis of systolic algorithms for pattern matching based on dynamic programming. Two systolic algorithms (HADP and HADPS) are proposed. The algorithm HADP designed by the projection method has no constraint on using processing elements, while the HADPS has the fixed array size p*q PE's, where p and q are any small constants. The proposed algorithms are considered to hold real time feature which is a important factor in pattern matching. 3. A processor array with separable global buses(PAP_b) is suggested to use for the problems where the global communication is effective to reduce the computation time. The PAP_b consists of N processing felements(PEs) and has global buses in each row and each column, and on each bus there are some switching units controlled by certain pe. algorithms for solving semigroup computations and z-selection on the PAP_b are described and evaluated to compare the results on the processor arrays with conventional global buses.
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