1989 Fiscal Year Final Research Report Summary
Computer Aided Design of Multiple-Valued Logic Networks Using Pass Transistors
| Project/Area Number |
62550268
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | University of the Ryukyus |
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Principal Investigator |
AFUSO Chushin Univ.of the Ryukyus, Fac.of Eng., Professor, 工学部, 教授 (30007033)
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| Co-Investigator(Kenkyū-buntansha) |
ZUKERAN Chotei Univ.of the Ryukyus, Fac.of Eng., Associate Professor, 工学部, 助教授 (50045019)
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| Project Period (FY) |
1987 – 1989
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| Keywords | Pass transistor / Multiple-valued logic circuit / U-gate / CAD / 回路網合成 |
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| Research Abstract |
A quaternary logic function is realized by pass transistor circuits in two ways: direct-driven pass transistors and literal-driven pass transistors. In the first method an n-variable quaternary logic function is divided into four partial functions, each of which outputs one of quaternary logic values (0,1,2,3). Then each partial function expressed in terms of literal,MAX and MIN is simplified and realized by direct-driven pass transistors. The circuits for partial functions so obtained are wire-ORed along with at most 6 transistors for short-circuit prevention. In particular, any negative function can be realized efficiently without short-circuit-preventing transistors.
As new types of gates, quaternary M-MOR, M-NAND and U-gate are proposed. The first two gates consist of direct-driven pass transistors and their circuit structures are identical,and each gate consists of 6 MOS-FET's of which corresponding 4 FET's are exactly the same in their size (W/L) and threshold voltages. The U-gate
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is a variable threshold gate based on the literal-driven pass transistors, and it consists of 8 MOS-FET's. The U-gate and constants (0,1,2,3) constitute a complete set of quaternary operators. The circuit consisting of 3 U-gates generates logic functions as many as 60% of all the one-variable functions when four inputs are kept at 0,1,2 and 3 while the threshold control input of each U-gate is varied. In order for this circuit to generate all the one-variable functions, 7 combinations of the 4 inputs are sufficient. Also, it is possible to obtain useful functions by directly driving the threshold control input with quaternary signal, and the network realization based on this scheme is left for future study. Computer simulation of the circuit performance by FSPICE shows that the literal-driven pass transistor circuits are superior to the direct-driven pass transistor circuits in both speed and power dissipation.
In terms of common functions an arbitrary quaternary logic function can be realized systematically in the form of U-gate, CP-gate and T-gate networks. The synthesis procedures are carried out fast on a personal computer including resulting logic circuit diagram displayed on the CRT. Less
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