1988 Fiscal Year Final Research Report Summary
Development of a High-speed 3-Dimensional Graphics System Utilizing Hierarchical Parallel Processing
| Project/Area Number |
62850059
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| Research Category |
Grant-in-Aid for Developmental Scientific Research
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | Kyoto University |
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Principal Investigator |
HAGIWARA Hiroshi Kyoto University, Faculty of Engineering, 工学部, 教授 (00025818)
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| Co-Investigator(Kenkyū-buntansha) |
INOUE Tomoko Kyoto University, Faculty of Engineering, 工学部, 教務職員 (40109145)
NIIMI Haruo Kyoto University, Faculty of Engineering, 工学部, 助手 (40144331)
SHIBAYAMA Kiyoshi Kyoto University, Faculty of Engineering, 工学部, 助教授 (70127091)
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| Project Period (FY) |
1987 – 1988
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| Keywords | 3-Dimensional Graphics / Graphics Systems / Parallel Processing / Multiprocessors / Special-purpose processors / 形状処理 / ソリッドモデリング |
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| Research Abstract |
This research is aiming at realizing a high-performance graphic information system whih can provide both high quality 3-dimensional solid modeling images and a real-time response time. To achieve this research goal, we utilized hierarchical parallel processings and system architectures with special purpose processor elements. The details are as follows.
1. At first, we investigated seceral hidden-surface algorithms for 3-dimensional scenes, and chose the scan-line algorithm because of its high efficiency. We them found that they would be more effective to divide the algorithm into two succeeding processing stages, and to introduce parallel processing to each of the two respectively.
2. We developed two types of special purpose processor elements, the SLP and the PXP. They are so designed to be suitable for each of the two prcessing stages, and are controlled by horizontal-type microinstructions respectively. This provides a flexible way to make the best use of their various special purpose hardware.
3. We also deceloped the firmware for 3-dimensional graphics on the SLP and the PXP. The firmware combines the scan-line algorithm with the smooth-shading and the shadowing processes. It also introduces a novel anti-aliasing method and a unique load distribution method. To improve productivity of the firmware, we implemented high-level micro-assembly languages and their processing systems.
4. We build a prototype machine with 2 SLP's and 4 pxp's to evaluate the capability of the system. The result showed that our aim can be achieved with a system of a practical size of configuration.
5. Furthermore, we designed a binary tree-like structured multiprocessor system to speed up the solid definition process which is a front end process to the displaying process. We confirmed that this design is very efficient especially for the set operations between objects which inbolves the largest amount of computation.
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