1989 Fiscal Year Final Research Report Summary
SYSTEMATIC STUDY ON THEORY AND TECHNOLOGY OF HIGHLY PARALLEL DIGITAL SIGNAL PROCESSING
| Project/Area Number |
63302035
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| Research Category |
Grant-in-Aid for Co-operative Research (A)
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| Allocation Type | Single-year Grants |
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| Research Field |
計測・制御工学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
HIGUCHI Tatsuo TOHOKU UNIVERSITY FACULTY OF ENGINEERING PROFESSOR, 工学部, 教授 (20005317)
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| Co-Investigator(Kenkyū-buntansha) |
NISHIHARA Akinori TOKYO INSTITUTE OF TECHNOLOGY, INTERNATIONAL COOPERATION CENTER FOR SCIENCE AND, 国際交流センター, 助教授 (90114884)
NISHIKAWA Kiyoshi KANAZAWA UNIVERSITY FACULTY OF ENGINEERING ASSOCIATE PROFESSOR, 工学部, 助教授 (40019774)
YASUURA Hiroto KYOTO UNIVERSITY FACULTY OF ENGINEERING ASSOCIATE PROFESSOR, 工学部, 助教授 (80135540)
NISHI Tetsuo KYUSHU UNIVERSITY FACULTY OF ENGINEERING PROFESSOR, 工学部, 教授 (40037908)
KAWAMATA Masayuki TOHOKU UNIVERSITY FACULTY OF ENGINEERING ASSOCIATE PROFESSOR, 工学部, 助教授 (70153004)
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| Project Period (FY) |
1988 – 1989
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| Keywords | Highly Parallel Signal Processing / Multidimensional Digital Signal Processing / 3-D Digital Filter / Multiple-Valued Arithmetic Circuit / Hardware Algorithm / 3-D signal |
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| Research Abstract |
In most real-time digital signal processing application, general-Purpose parallel computers cannot offer satisfactory processing speed. Particularly, the increasing demands of speed and performance in two-dimensional (2-D) or three-dimensional (3-D) signal applications necessitate a revolutional computing technology. This project is to study systematically on theory and technology of highly parallel digital signal processing in real-time, which includes the following contents : basic theory, hardware algorithms, and architecture design for highly parallel signal processing.
The project begins with basic theory of 2-D and 3-D digital filters and discrete Fourier transform. In order to develop multidimensional digital signal processing, it is needed not only to develop hardware, but also to search efficient design techniques. The investigators propose a design technique of 2-D and 3-D separable denominator digital filters based on the reduced-dimensional decomposition design. Thus computational effort needed in the design procedure can be reduced.
In real-time signal processing, realization of high speed in adder and multiplier is most important. This project gives a new hardware algorithm based on the signed-digit (SD) number. In the SD number representation, catry propagation during addition and subtraction is always limited to one position to the left. This property of the number system is very useful not only for addition but also for multiplication. Practically, adder and multiplier are designed using multiplevalued current-mode circuit and implemented in CMOS technology. It is confirmed that the adder and multiplier obtained here are superior to the fastest binary ones in term of speed. Finally, highly parallel processing architecture is studied and designed in 2-D and 3-D digital filters. Board implementation of proposed architecture is carried out. The system is successfully applied to real-time application of 2-D and 3-D signals.
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