Organic nonvolatile memory transistors based on fullerene and an electron-trapping polymer
Graphical abstract
Highlights
► We report organic n-type nonvolatile memory transistors based on a fullerene semiconductor. ► The memory transistor can be programmed/erased by applying gate voltage pulses of 50/−45 V. ► The memory transistor shows a memory window 10 V and a retention time over 105 s. ► The memory effect originates from trapping and detrapping electrons at a CYTOP/SiO2 interface.
Introduction
Electronics using organic materials has rapidly grown due to their unique and attractive features including mechanical flexibility, low-cost and low temperature manufacturing, which are suitable for large area fabrication [1], [2], [3], [4], [5], [6], [7], [8], [9], [10]. Various types of organic electronic device, such as organic solar cells [1], [2], organic light-emitting diodes [3], [4], organic field-effect transistors (OFETs) [5], [6], and organic integrated circuits [7], [8], have been fabricated. Memory devices have received considerable attention because they can be used for data/code storage in electronic circuits and as radio frequency identification tags and microprocessors [9], [10]. Memory effects can be observed in capacitor [11], resistor [12], and transistor [13] structures. Among these organic memories, transistor memories have gained considerable attention in recent years because they require the use of a single transistor structure, without loss of reading behavior; moreover, these memories can be easily embedded in integrated circuits [14], [15], [16]. The memory effects can be realized by using ferroelectric polymers such as poly (vinylidenefluoride/trifluoroethylene) [17], [18]. Polarization/depolarization of the gate dielectrics would induce/deplete carriers in the transistor channel, corresponding to the logic states. However, it is hard to obtain long retention time from the devices reported thus far because of the rough surface and high leakage current of the gate ferroelectric film [15], [17], [18], [19]. Another approach for constructing the organic memory transistors is to employ metals [19], [20] or nanoparticles (NPs) [20], [21] as floating gates. Under an external field, charges are injected and stored into the floating gate that is isolated by two insulators. Information can be presented via charge storage in the floating gate. However, fabrication of the inorganic floating gates requires vacuum evaporation of metals or other complicated processes [19], [20], [21], which are not compatible for low cost manufacturing of organic memories.
Recently, electron-trapping polymers were demonstrated as substituted candidates for charge storage media. The memory transistors fabricated based on these materials exhibited high stability of data storage [23], [24]. Moreover, because of the solution processability of these polymers, the memory devices based on them can be prepared by low-temperature fabrication; hence, the electron-trapping polymers offer promising applications in future electronic nonvolatile memory technologies. Structurally, an electron-trapping polymer is embedded as a second dielectric in a conventional pentacene transistor. Under the influence of an external field, mobile electrons are injected and captured in a thin layer of the electron-trapping polymer or at the interface between the two dielectrics [15]. The captured electrons are stable even after the electric field is removed, and this phenomenon is referred to as the nonvolatile memory effect. To release the trapped electrons, a reverse voltage must be applied to the device. Similar to the case of a floating-gate memory, charge trapping and detrapping at the trap sites modulate the conductivity of the transistor channel, resulting in different current levels. Therefore, the digital information can be encoded by the channel current levels. Baeg et al. fabricated a poly(α-methylstyrene) (PαMS)-based pentacene memory transistor with program/erase voltages of 200/−100 V [24]. Guo et al. fabricated polystyrene- or polymethylmethacrylate (PMMA)-based memory devices in which light-assisted programming and erasing processes were triggered at voltages of >40 V and −150 V, respectively [25]. Feng et al. observed a memory effect in transistors fabricated by dispersing nanostructured poly(9,9-dioctylfluorene) (PFO) in PMMA. However, a high voltage of 200 V and light illumination were required to function their memory transistors [26]. In such reported memory transistors, either pentacene [24], [25], [26] or copper phthalocyanine (CuPc) [25] has been used as an electron-transport layer (ETL) for the programming or erasing process. Obviously, the common drawback of these structures is that electrons must move through the pentacene and CuPc films with very low electron mobility, which results in very large switching voltages [23], [24], [25], [26]. For example, in pentacene-based OFETs, a field-effect electron mobility (0.005 cm2 V−1 s−1) is much lower than a field-effect hole mobility (0.1 cm2 V−1 s−1) [27]. For practical applications, the working voltages should be scaled down to the level as small as possible. Furthermore, the operation mechanism of the memory transistors has not yet been clarified, for example, the memory effect is attributed to charge trapping in the PαMS bulk or at the interface between PαMS and SiO2 [15]. To further understand the operation mechanism, the roles of the bulk and the interface in the memory effect must be clarified.
Fullerene (C60) has been widely used as a n-type semiconductor in OFETs [28] and as an ETL in organic electronics [29], [30] due to its high electron mobility. An Al electrode is suitable for injecting electrons into C60 because the Fermi level of Al (–4.3 eV) [12] is close to the lowest unoccupied molecular orbital (LUMO) level of C60 (–4.5 eV) [28], [29]. Thus, the combination of Al and C60 is ideal for reducing the working voltage and enhancing the performance of the memory devices with an electron-trapping polymer. However, an organic memory transistor using C60 has never been reported.
In this article, we demonstrate n-type organic memory transistors based on the floating-gate-like effect that originates from electron trapping at the interface between a poly(perfluoroalkenyl vinyl ether) (CYTOP) thin film and SiO2. In contrast to conventional approaches where a p-type semiconductor is used as the ETL, the present approach involves the use of C60 as the active layer and the CYTOP/SiO2 interface as the electron-trapping site, and hence, the working voltages of the memory devices can be significantly reduced. A shift in transfer characteristics of the transistors could be reversibly controlled by the applications of the external gate fields. Programming/erasing processes were realized by applying gate pulse voltages of 50/−45 V. These switching voltages were much lower than those mentioned in previous reports [24], [25], [26]. The devices had a large memory window of 10 V (ΔVth, defined as a difference in threshold voltage (Vth) between the programmed and erased states), a memory on/off ratio of 105, and a retention time of >105 s, indicating stable information storage in the memory devices. Additionally, analysis of the capacitance–voltage measurement of the metal–insulator–semiconductor capacitor using the layers of CYTOP/SiO2 and C60 revealed that the memory mechanism was ascribed to trapping/detrapping of electrons at the CYTOP/SiO2 interface.
Section snippets
Experimental
Fig. 1 shows a cross section and an optical image of the top view of the C60 OFETs with a bottom-gate top-source/drain contact geometry as well as the chemical structures of C60 and CYTOP. The memory transistor devices were fabricated on a heavily doped Si gate electrode (n+Si, resistivity: 1–100 Ωcm) coated with a 50 nm SiO2 dielectric layer. The silicon wafer was cleaned by ultrasonication (in acetone for 5 min, in detergent for 10 min, twice in pure water for 5 min, and in isopropanol for 10 min)
Results and discussion
Fig. 2 shows the typical electrical characteristics of the organic transistors. For the output behavior, the drain current (ID) of the transistors increased at a positive gate voltage (VG). In the linear region of the graph, ID showed a linear increase at a low drain voltage (VD), implying efficient electron injection at the C60/Al interface. Then, ID saturated at a high VD because the conducting channel was pinched off. These curves indicated that the transistor devices showed standard n-
Conclusions
In summary, we have demonstrated low-working-voltage and long-lifetime n-type memory transistors based on C60 and CYTOP. The transistors showed very good n-type performance with a Vth of 2.8 V and a μ of 0.4 cm2 V−1 s−1, respectively. The ID of the transistors was modulated by trapping/detrapping of electrons at the CYTOP/SiO2 interface (a floating-gate-like memory effect). The required program/erase voltages were 50/−45 V, which resulted in a large ΔVth of 10 V. An on/off ratio of 105 was obtained
Acknowledgement
The authors thank Prof. Heisuke Sakai (Waseda University) for fruitful discussion. This work was partially supported by a Grant-in-Aid (Grant No. 20241034) and Scientific Research on Innovative Areas “pi-Space” (Grant No. 20108012) from the Ministry of Education, Culture, Sports, Science, and Technology, Japan. T. T. D. gratefully acknowledges financial support by a 322 Scholarship (doctoral course) of the Vietnamese Government.
References (38)
- et al.
Org. Electron.
(2012) - et al.
Org. Electron.
(2011) - et al.
Org. Electron.
(2012) - et al.
Org. Electron.
(2012) - et al.
Org. Electron.
(2010) - et al.
Org. Electron.
(2008) - et al.
Adv. Funct. Mater.
(2011) - et al.
Adv. Funct. Mater.
(2011) - et al.
Appl. Phys. Lett.
(2009) - et al.
Nature (London)
(2000)
Nature (London)
Adv. Mater.
Adv. Mater.
IEEE Electron Device Lett.
Appl. Phys. Lett.
Adv. Mater.
Chem. Mater.
Solid-State Electron.
J. Appl. Phys.
Cited by (38)
Location-dependent multi-parameter detection behaviors using hetero-interfaced organic anti-ambipolar phototransistors
2021, Sensors and Actuators A: PhysicalCitation Excerpt :The length and width of the channel were 1,000 μm and 2,200 μm, respectively. Finally, we encapsulated the devices with Cytop to prevent the deterioration of the characteristics by air exposure [40–42]. For the HI-AA phototransistor, Cytop-coated Si/SiO2 was prepared.
Low switching voltage, high-stability organic phototransistor memory based on a photoactive dielectric and an electron trapping layer
2020, Organic ElectronicsCitation Excerpt :To measure the retention time, the on-state or off-state currents were continuously recorded at VD of −2 V with zero gate bias under dark. As shown in Fig. 4(a), the retention characteristics were quite stable, such that the on/off ratio only decreased from 1.8 × 105 to ~105 after 2 × 106 s (23 days), which is the largest ratio ever reported [1,2,5–36]. An endurance test of the devices was conducted to examine the reliability of the phototransistor memory.
Structural parameters affecting the performance of non-volatile memory based on organic field-effect transistors
2019, Microelectronic EngineeringStable charge retention in graphene-MoS<inf>2</inf> assemblies for resistive switching effect in ultra-thin super-flexible organic memory devices
2018, Organic ElectronicsCitation Excerpt :The advantages of polymer memory that put them ahead in the list, include advanced features like flexibility, solution processing and 3D-stacking capability in addition to its lower cost of fabrication, higher scalability, light weight and environment friendly natures [4]. The origin of scientific interest can be credited to the bistable resistance states of polymer that can be tuned by embedding inorganic nanoparticles that act as the charge trapping centres and carrier transporting medium, whereas the insulating polymer serves as the blocking matrix of the charge carriers [4–6]. The hybrid composite approach has been found quite beneficial to effectively improve the memristive parameter indices like ON/OFF current ratio, switching speed, power consumption, retention time, stability and reproducibility etc [7–10].
Effect of thickness on bistable switching characteristics of a pentacene based memory device
2018, Materials Today: ProceedingsMulti-level non-volatile organic transistor-based memory using lithium-ion-encapsulated fullerene as a charge trapping layer
2017, Organic ElectronicsCitation Excerpt :The advantage of both the NPs floating gate and the charge-trap polymer memory OFETs lies in their simple fabrication process. In addition, the solution process ability and low temperature fabrication process are suitable for low cost and large-area fabrication [24–26]. Expansion of the storage capacity of memory OFETs could be done by producing multi-level memory OFET, which exhibited several ON states [21–26].