| Budget Amount *help |
¥286,130,000 (Direct Cost: ¥220,100,000、Indirect Cost: ¥66,030,000)
Fiscal Year 2017: ¥60,190,000 (Direct Cost: ¥46,300,000、Indirect Cost: ¥13,890,000)
Fiscal Year 2016: ¥60,190,000 (Direct Cost: ¥46,300,000、Indirect Cost: ¥13,890,000)
Fiscal Year 2015: ¥60,190,000 (Direct Cost: ¥46,300,000、Indirect Cost: ¥13,890,000)
Fiscal Year 2014: ¥63,440,000 (Direct Cost: ¥48,800,000、Indirect Cost: ¥14,640,000)
Fiscal Year 2013: ¥42,120,000 (Direct Cost: ¥32,400,000、Indirect Cost: ¥9,720,000)
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| Outline of Final Research Achievements |
We have developed 3-dimentional pixel process which combines sensor and circuit in a Silicon-On-Insulator (SOI) wafer. By introducing a new double SOI technology, we could solve the problem of interference between sensor and circuit, radiation tolerance, charge collection efficiency and so on. Furthermore, we succeeded to reduce leakage current of sensors by adding a pinning layer under Buried Oxide (BOX) layer, and we named this a Pinned Depleted Diode (PDD) structure.
We have also developed Super-Steep transistors, which have very steep Id-Vg characteristic. This is very useful to realize very low-power circuit.
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