TAKEZAWA Toshiyuki ATR Interpreting Telephony Research Laboratories
KASAHARA Yoshinori associate professor school of Science and Engineering, Waseda University, 理工学部, 助教授 (30152622)
KOBAYASHI Tetsunori associate professor School of science and Engineering, Waseda University, 理工学部, 助教授 (30162001)
MATSUMOTO Takashi professor School of Science and Engineering, Waseda University, 理工学部, 教授 (80063767)
AKIZUKI Kageo professor School of Science and Engineering, Waseda University, 理工学部, 教授 (10063603)
|Budget Amount *help
¥6,600,000 (Direct Cost : ¥6,600,000)
Fiscal Year 1993 : ¥800,000 (Direct Cost : ¥800,000)
Fiscal Year 1992 : ¥2,600,000 (Direct Cost : ¥2,600,000)
Fiscal Year 1991 : ¥3,200,000 (Direct Cost : ¥3,200,000)
We have already researed the VLSI design system (SYARDS) based on high-level description for 5 years before this project. Besides, This system was evaluated through a connection with the existing VLSI ligic-level synthesis tool. The connection showed possibilities of the high-level synthesis systems like SYARDS.In this project, this system is advanced and generalized in order to implement the system including the design environment, which aims not only processor design but also its application. Moreover, this project is proceeded for the purpose of founding the high-level design technology. Definitely, we deal with problems on the improvement of the specification description language including concurrent processings, its analysis system, and the scheduling and simulator in operation level.
As another subject in the project, the design of a double layr parallel network is considered. This research is carried out by Takashi Matsumoto, and important results on a layred architecture for reg
ularization neuro chips are acquired.
The application specification processors which executes the algorithms described in high-level languages (Pascal or C) can automatically be designed using the design system (SYARDS). For 3-year term of project, we strengthen the performance of SYARDS through the optimal design method using the extraction of local parallelism including algorithms, the support technology for bit-width determination, which is needed in dealing with the realistic algorithms for digital signal processing, the introduction of concurrent processing description with C language, and the optimization on the pipeline designs.
During the term of project, the concept of co-design is indicated in processor design which considers from both sides of hardware and software. However, this system is originally characterized to design compilers which generate its software as well as hardware. Therefore, this project is also close to the methodology of co-design.
In the future, SYARDS will be extended to the direction like this, and the results of this project are considered to have a great deal of significance for the future VLSI design technology. Less