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Study on Post-Binary ULSI Sstems

Research Project

Project/Area Number 04044024
Research Category

Grant-in-Aid for international Scientific Research

Allocation TypeSingle-year Grants
SectionJoint Research
Research InstitutionTohoku University, Graduate School of Information Sciences

Principal Investigator

KAMEYAMA Michitaka  Tohoku University, Graduate school of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (70124568)

Co-Investigator(Kenkyū-buntansha) SILIO Charle  メリーランド大学, 電気工学科, 助教授
BUTLER Jon T.  Naval Postgraduate School, Department of Computer Science, 教授
SMITH Kenneth C.  Toronto University, Department of Computer Science, 計算機学科, 教授
SASAO Tsutomu  Kyusyu Institute of Technology, Faculty of Information Engineering, 情報工学部, 教授 (20112013)
HANYU Takahiro  Tohoku University, Graduate school of Information Sciences, 情報科学研究科, 助教授 (40192702)
HIGUCHI Tatsuo  Tohoku University, Graduate school of Information Sciences, 情報科学研究科, 教授 (20005317)
SILIO Carles B.  Maryland University, Department of Electrical Engineering
CHARLES B Si  メリーランド大学, 助教授
JON T Butler  Naval Postgraduate School, 教授
KENNETH C Sm  トロント大学, 教授
Project Period (FY) 1992 – 1993
Project Status Completed (Fiscal Year 1993)
Budget Amount *help
¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 1993: ¥1,200,000 (Direct Cost: ¥1,200,000)
Fiscal Year 1992: ¥2,200,000 (Direct Cost: ¥2,200,000)
KeywordsIntelligent Integrated Systems / Highly Parallel Multiple-Valued Arithmetic and Logic Circuits / Linear Digital System / Ultra Fine Integrated Circuits / Small Critical-Delay Path / Small Interconnection Delay / Device-Model Based Electronics / Multiple-Valued Integrated Devices / 多値情報処理 / 高並列演算回路 / 専用VLSIプロセッサ / 多値集積回路 / 空間的並列構造プロセッサ
Research Abstract

The present binary VLSI systems will be confronted with many serious problems in an ultimately fine geometry feature size. Some of them are listed below :
(1) Interconnection delay is prominent limit on the performance in the deep submicron integrated circuits.
(2) For low-voltage operations, noises caused inside a chip should be reduced.
(3) Parallel procesing performance is limited by data communications between processing elements.
(4) Large scale design is essential at various levels such as logic design, test, circuit design and physical design.
(5) New phenomena such as tunnneling and quantum effects will be caused in microelectronics devices, which is usually assumed to be inconvenient effects for binary digital operations.
Multiple-valued digital processing and its integration are expected to be one of the most effective solutions for the above problems. The objective of this research is to demonstrate theories, new developments and techniques in multiple-valued integrated circuits a … More nd their applications. Especially, the delay time due to global communications between functional modules is one of the most important factors to determine the total performance In ULSI Processors for the applications of intelligent integrated systems.
Several concrete advantages of multiple-valued digital procssing technology have been established in deep submicron geometry. They are classified to the device and circuit level, the arithmetic and logic algortihm level, and the system application level. In the device and circuit level, we have demonstrated that the new area called device-model based electronics becomes very important to activate the new direction of the device development suitable for multiple-valued operations. In the alogorithm level, we have proposed a new design method for highly parallel operation circuits based on a linear concept. In the system application level, we have designed a new multiple-valued ULSI processor for digital control with spatially parallel structure. Further, we have proposed a universal super chip for intelligent integrated systems with very flexible network structure. Less

Report

(2 results)
  • 1993 Final Research Report Summary
  • 1992 Annual Research Report
  • Research Products

    (28 results)

All Other

All Publications (28 results)

  • [Publications] Katsuhiko Shimabukuro: "Design of a Multiple-Valued VLSI Processor for Digital Control" Trans.IEICE. E75-D. 709-717 (1992)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Beyond-Binary Circuits for Signal Processing" Digest of IEEE Int.Solid-State Circuits Conference. 134-135 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Prospects of Multiple-Valued VLSI Processors" Trans.IEICE. E76-C. 383-392 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Takeshi Kasuga: "Design of Robust-Fault-Tolerant Multiple-Valued Arithmetic Circuits and Their Evaluation" Trans.IEICE. E76-C. 428-435 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Makoto Honda: "Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation" Trans.IEICE. E76-C. 455-462 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Katsuhiko Shimabukuro: "Architecture of a Parallel Multiple-Valued Arithmetic VLSI Processor Using Adder-Based Processing Elements" Trans.IEICE. E76-C. 463-471 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Saneaki Tamaki: "Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinational Circuits Based on Partition Theory" Trans.IEICE. E76-D. 548-554 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Saneaki Tamaki: "Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel K-Ary Operation Circuits" Trans.IEICE. E76-C. 1112-1118 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Masami Nakajima: "Design of Highly Parallel Linear Digital System for ULSI Processors" Trans.IEICE. E76-C. 1119-1125 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model" Trans.IEICE. E76-C. 1126-1132 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Michitaka Kameyama: "Prospects of Multiple-Valued ULSI Processors" Proc.of the Int.Conference on Advanced Microelectronics Devices and Processing. 777-784 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Katsuhiko Shimabukuro: "Design of a Multiple-Valued VLSI Processor for Digital Control" Trans.IEICE. E75-D. 709-717 (1992)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Beyond-Binary Circuits for Signal Processing" Digest of IEEE Int. Solid-State Circuits Conference. 134-135 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Prospects of Multiple-Valued VLSI Processors" Trans.IEICE. E76-C. 382-392 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Takeshi Kasuga: "Design of Robust-Fault-Tolerant Multiple-Valued Arithmetic Circuits and Their Evaluation" Trans.IEICE. E76-C. 428-435 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Makoto Honda: "Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation" Trans.IEICE. E76-C. 455-462 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Katsuhiko Shimabukuro: "Architecture of a Parallel Multiple-Valued Arithmetic VLSI Processor Using Adder-Based Processing Elements" Trans.IEICE. E76-C. 463-471 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Saneaki Tamaki: "Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinational Circuits Based on Partition Theory" Trans.IEICE. E76-D. 548-554 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Saneaki Tamaki: "Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel K-Ary Operation Circuits" Trans.IEICE. E76-C. 1112-1118 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Masami Nakajima: "Design of Highly Parallel Linear Digital System for ULSI Processors" Trans.IEICE. E76-C. 1119-1125 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model" Trans.IEICE. E76-C. 1126-1132 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] Michitaka Kameyama: "Prospects of Multiple-Valued ULSI Processors" Proc. of the Int. Conference on Advanced Microelectronics Devices and Processing. 777-784 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] M.HONDA: "Residue Arithmetic Based Multiple-Values VLSI Image Processor" Proceedings of the IEEE International Symposium on Multiple-Valued Logic. 330-336 (1992)

    • Related Report
      1992 Annual Research Report
  • [Publications] S.TAMAKI: "Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinational Circuits" Proceedings of the IEEE International Symposium on Multiple-Valued Logic. 382-388 (1992)

    • Related Report
      1992 Annual Research Report
  • [Publications] 矢部 義一: "共鳴トンネルダイオードモデルに基づく3値Tゲートの構成" 平成4年度電気関係学会東北支部連合大会. 35 (1992)

    • Related Report
      1992 Annual Research Report
  • [Publications] 中島 雅美: "局所演算性を有する単項演算線形ディジタルシステムの統一的設計" 平成4年度電気関係学会東北支部連合大会. 159 (1992)

    • Related Report
      1992 Annual Research Report
  • [Publications] K.SHIMABUKURO: "Design of a Multiple-Valued VLSI Processor for Digital Control" IEICE Trasactions on Information & Systems. E75-D. 709-717 (1992)

    • Related Report
      1992 Annual Research Report
  • [Publications] T.HANYU: "Beyond-Binory Circuits for Signal Processing" Digest of 1993 IEEE International Solid-State Circuits Conference. 134-135 (1993)

    • Related Report
      1992 Annual Research Report

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Published: 1992-04-01   Modified: 2016-04-21  

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