Grant-in-Aid for Overseas Scientific Survey.
|Research Institution||Tohoku University, Graduate School of Information Sciences|
KAMEYAMA Michitaka Tohoku University, Graduate school of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (70124568)
CHARLES B Si メリーランド大学, 助教授
JON T Butler Naval Postgraduate School, 教授
KENNETH C Sm トロント大学, 教授
笹尾 勤 九州工業大学, 情報工学部, 教授 (20112013)
樋口 龍雄 東北大学大学院, 情報科学研究科, 教授 (20005317)
SILIO Charle メリーランド大学, 電気工学科, 助教授
BUTLER Jon T Naval Postgraduate School, 教授
SMITH Kennet トロント大学, 計算機学科, 教授
羽生 貴弘 東北大学大学院, 情報科学研究科, 助教授 (40192702)
SASAO Tsutomu Kyusyu Institute of Technology, Faculty of Information Engineering
SMITH Kenneth C. Toronto University, Department of Computer Science
HIGUCHI Tatsuo Tohoku University, Graduate school of Information Sciences
HANYU Takahiro Tohoku University, Graduate school of Information Sciences
SILIO Carles B. Maryland University, Department of Electrical Engineering
BUTLER Jon T. Naval Postgraduate School, Department of Computer Science
|Project Fiscal Year
1992 – 1993
Completed(Fiscal Year 1993)
|Budget Amount *help
¥3,400,000 (Direct Cost : ¥3,400,000)
Fiscal Year 1993 : ¥1,200,000 (Direct Cost : ¥1,200,000)
Fiscal Year 1992 : ¥2,200,000 (Direct Cost : ¥2,200,000)
|Keywords||Intelligent Integrated Systems / Highly Parallel Multiple-Valued Arithmetic and Logic Circuits / Linear Digital System / Ultra Fine Integrated Circuits / Small Critical-Delay Path / Small Interconnection Delay / Device-Model Based Electronics / Multiple-Valued Integrated Devices / 知能集積システム / 高並列多値演算回路 / 線形ディジタルシステム / 超微細集積回路 / 微小クリティカルパス遅延 / 微小配線遅延 / デバイスモデルベーストエレクトロニクス / 多値集積デバイス / 多値情報処理 / 高並列演算回路 / 専用VLSIプロセッサ / 多値集積回路 / 空間的並列構造プロセッサ|
The present binary VLSI systems will be confronted with many serious problems in an ultimately fine geometry feature size. Some of them are listed below :
(1) Interconnection delay is prominent limit on the performance in the deep submicron integrated circuits.
(2) For low-voltage operations, noises caused inside a chip should be reduced.
(3) Parallel procesing performance is limited by data communications between processing elements.
(4) Large scale design is essential at various levels such as logic design, test, circuit design and physical design.
(5) New phenomena such as tunnneling and quantum effects will be caused in microelectronics devices, which is usually assumed to be inconvenient effects for binary digital operations.
Multiple-valued digital processing and its integration are expected to be one of the most effective solutions for the above problems. The objective of this research is to demonstrate theories, new developments and techniques in multiple-valued integrated circuits a
nd their applications. Especially, the delay time due to global communications between functional modules is one of the most important factors to determine the total performance In ULSI Processors for the applications of intelligent integrated systems.
Several concrete advantages of multiple-valued digital procssing technology have been established in deep submicron geometry. They are classified to the device and circuit level, the arithmetic and logic algortihm level, and the system application level. In the device and circuit level, we have demonstrated that the new area called device-model based electronics becomes very important to activate the new direction of the device development suitable for multiple-valued operations. In the alogorithm level, we have proposed a new design method for highly parallel operation circuits based on a linear concept. In the system application level, we have designed a new multiple-valued ULSI processor for digital control with spatially parallel structure. Further, we have proposed a universal super chip for intelligent integrated systems with very flexible network structure. Less