| Project/Area Number | 04044024 |
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| Research Category |
Grant-in-Aid for international Scientific Research
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| Allocation Type | Single-year Grants |
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| Section | Joint Research |
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| Research Institution | Tohoku University, Graduate School of Information Sciences |
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Principal Investigator |
KAMEYAMA Michitaka Tohoku University, Graduate school of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (70124568)
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| Co-Investigator(Kenkyū-buntansha) |
SILIO Charle メリーランド大学, 電気工学科, 助教授
BUTLER Jon T. Naval Postgraduate School, Department of Computer Science, 教授
SMITH Kenneth C. Toronto University, Department of Computer Science, 計算機学科, 教授
SASAO Tsutomu Kyusyu Institute of Technology, Faculty of Information Engineering, 情報工学部, 教授 (20112013)
HANYU Takahiro Tohoku University, Graduate school of Information Sciences, 情報科学研究科, 助教授 (40192702)
HIGUCHI Tatsuo Tohoku University, Graduate school of Information Sciences, 情報科学研究科, 教授 (20005317)
SILIO Carles B. Maryland University, Department of Electrical Engineering
CHARLES B Si メリーランド大学, 助教授
JON T Butler Naval Postgraduate School, 教授
KENNETH C Sm トロント大学, 教授
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| Project Period (FY) |
1992 – 1993
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| Project Status |
Completed(Fiscal Year 1993)
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| Budget Amount *help |
¥3,400,000 (Direct Cost : ¥3,400,000)
Fiscal Year 1993 : ¥1,200,000 (Direct Cost : ¥1,200,000)
Fiscal Year 1992 : ¥2,200,000 (Direct Cost : ¥2,200,000)
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| Keywords | Intelligent Integrated Systems / Highly Parallel Multiple-Valued Arithmetic and Logic Circuits / Linear Digital System / Ultra Fine Integrated Circuits / Small Critical-Delay Path / Small Interconnection Delay / Device-Model Based Electronics / Multiple-Valued Integrated Devices / 多値情報処理 / 高並列演算回路 / 専用VLSIプロセッサ / 多値集積回路 / 空間的並列構造プロセッサ |
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| Research Abstract |
The present binary VLSI systems will be confronted with many serious problems in an ultimately fine geometry feature size. Some of them are listed below :
(1) Interconnection delay is prominent limit on the performance in the deep submicron integrated circuits.
(2) For low-voltage operations, noises caused inside a chip should be reduced.
(3) Parallel procesing performance is limited by data communications between processing elements.
(4) Large scale design is essential at various levels such as logic design, test, circuit design and physical design.
(5) New phenomena such as tunnneling and quantum effects will be caused in microelectronics devices, which is usually assumed to be inconvenient effects for binary digital operations.
Multiple-valued digital processing and its integration are expected to be one of the most effective solutions for the above problems. The objective of this research is to demonstrate theories, new developments and techniques in multiple-valued integrated circuits a
… More
nd their applications. Especially, the delay time due to global communications between functional modules is one of the most important factors to determine the total performance In ULSI Processors for the applications of intelligent integrated systems.
Several concrete advantages of multiple-valued digital procssing technology have been established in deep submicron geometry. They are classified to the device and circuit level, the arithmetic and logic algortihm level, and the system application level. In the device and circuit level, we have demonstrated that the new area called device-model based electronics becomes very important to activate the new direction of the device development suitable for multiple-valued operations. In the alogorithm level, we have proposed a new design method for highly parallel operation circuits based on a linear concept. In the system application level, we have designed a new multiple-valued ULSI processor for digital control with spatially parallel structure. Further, we have proposed a universal super chip for intelligent integrated systems with very flexible network structure. Less
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