Research on Single Electron Tunnel Device using substrates with small misorientations
Grant-in-Aid for General Scientific Research (B)
|Allocation Type||Single-year Grants|
|Research Institution||Toyo University|
SUGANO Takuo Toyo University, Electric and Electronics, Professor, 工学部, 教授 (50010707)
KANDA Yozo Toyo University, Electric and Electronics, Professor, 工学部, 教授 (70041845)
MURAYAMA Yoichi Toyo University, Electric and Electronics, Professor, 工学部, 教授 (40057956)
|Project Period (FY)
1993 – 1995
Completed(Fiscal Year 1995)
|Budget Amount *help
¥7,400,000 (Direct Cost : ¥7,400,000)
Fiscal Year 1995 : ¥900,000 (Direct Cost : ¥900,000)
Fiscal Year 1994 : ¥1,600,000 (Direct Cost : ¥1,600,000)
Fiscal Year 1993 : ¥4,900,000 (Direct Cost : ¥4,900,000)
|Keywords||Small misorientation substrate / Step-terrace structure / anisotropic etching / Surface inversion layr / Single electron transistor / Quantum dot / Ultra-fine pattern / Asymmetric tunnel barrier / シングル・エレクトロニクス / 単一電子デバイス / クーロン・ブロッケイド / トンネル現象 / クーロン・ブロッケード|
(1) Formation of step-terrace structures using Si surface with small misorientations
Formatio of Single or Double atomiclayr steps was achieved with high cotrollability by annealing of Si (100) substrates with small misorientations under ultra-high vacuum condition. Samples were heated by passing current through them and the misorientation angles of Si (100) substrates are 4ﾟ and 1ﾟ toward (110) direction.
(2) Design and fablication of single electron transistor using a small island surrounded by group of surfaces with same orientation
The fablication process of single electron transistor favarable for dense integration was proposed. Principle points of this fablication process were as followed. Firstly, the inversion layr formed by electric field was used for quantum dot. Secondly, the area of inversion layr was reduced using recess structure surrounded by (111) surfaces with single or double atomiclayr steps. Finally, the recess structure was fablicated by both anisotropic etching of Si
(100) substarte and annealing the substrate under ultara-high vacuum condition.
Device performance of this single electron transistor was simulated by 2-dimentional capacitance analysis and the optimum device scale was estimated. Single electron transistor with this scale was fablicated and its electrical properties also characterized.
In addition, electron beam lithography process was examined for further scale down of this device and fablication of 0.05mum line pattern was achieved.
(3) Design and fablication of single electron device with asymmetric tunnel barrier
Single electron device with asymmetric tunnel barrier was proposed and its performance was simulated. It was demonstrated that directionality of tunneling current and less correlation between capacitance and resistanece makes it easy to fablicate single electron device with high performance.
Furthermore, it was made clear that asymmetric tunnel barrier have advantages for realizing of not only boolean logic but also non boolean logic like binary decission diagram (BDD). Less
Research Output (21results)