|Budget Amount *help
¥5,300,000 (Direct Cost : ¥5,300,000)
Fiscal Year 1996 : ¥2,700,000 (Direct Cost : ¥2,700,000)
Fiscal Year 1995 : ¥2,600,000 (Direct Cost : ¥2,600,000)
1. High Functional LSI and Gigascale Integrated System realized by four-terminal device
We have realized elemental circuits for an intelligent electronic system by using a four-terminal device, Neuron-MOS (vMOS), as an elemental device. Test circuits were designed, fabricated and evaluated by the measurement of fabricated test circuits.
Real-time motion-vector detector and real-time center-of-mass tracer circuit have been developed by using vMOS.High-speed and high-accuracy analog non-volatile memory, vMOS correlator based on Manhattan distance computation, vMOS winner-take-all circuit, which are the key elements of intelligent event-recognition hardware, have been developed. By using the same architecture as the event-recognition hardware, we have developed a vector quantization (VQ) processor chip for real-time motion picture compression using digital circuit technology. The VQ chip exhibits 1,000 times superior speed performance compared to software realization using a microprocessor
2. Low Power Device / Circuit Technology for Gigascale Integration
Low power operation of the circuit is essential for gigascale integration. We have developed two new low-power circuit schemes for vMOS.One is a sense-amp vMOS logic circuit scheme, which is developed by applying a sense-amplifier to the vMOS logic decision circuit. The other is a deep-threshold vMOS scheme, in which deep threshold transistors and effectively-designed buffer circuit are utilized. Ta-gate SOI-MOSFET which exhibits high performance even with a 1V power supply has been developed. Extremely-low-power adiabatic logic circuit scheme has also been developed for the gigascale integrated circuit.
3. Limit to the gigascale integration
Opportunities for gigascale integration are governed by a hierarchy of physical limits whose five levels can be classified as : fundamental, material, device, circuit, and system. This distinctive methodology is extended by elucidating the impact on gigascale integration of random dopant atom placement in the channel region of a MOSFET.
4. Optimization of the system configuration
Based on a newly derived complete stochastic interconnect distribution, an optimal wiring network architecture is defined that minimizes chip area and power dissipation. Less