Grant-in-Aid for Scientific Research on Priority Areas (A)
|Research Institution||University of Tokyo|
ASADA Kunihiro Univ. of Tokyo, VLSI Design and Education Center, Professor, 大規模集積システム設計教育研究センター, 教授 (70142239)
NATORI Kenji Univ. of Tsukuba, Institute of Applied Physics, Professor, 物理工学系, 教授 (20241789)
KOYANAGI Mitsumasa Tohoku Univ., Graduate School of Engineering, Professor, 大学院・工学研究科, 教授 (60205531)
ISHIKAWA Masatoshi Univ. of Tokyo, Graduate School of Engineering, Professor, 大学院・工学系研究科, 教授 (40212857)
AIZAWA Kiyoharu Univ. of Tokyo, Graduate School of Frontier Science, Associate Professor, 新領域創生科学研究科, 助教授 (20192453)
YAGI Tetsuya Kyushu Ins. of Tech., Computer Sci. & Sys. Eng., Asso. Prof., 情報工学科, 助教授 (50183976)
|Project Fiscal Year
1995 – 1998
Completed(Fiscal Year 1998)
|Budget Amount *help
¥136,400,000 (Direct Cost : ¥136,400,000)
Fiscal Year 1998 : ¥24,700,000 (Direct Cost : ¥24,700,000)
Fiscal Year 1997 : ¥39,800,000 (Direct Cost : ¥39,800,000)
Fiscal Year 1996 : ¥32,800,000 (Direct Cost : ¥32,800,000)
Fiscal Year 1995 : ¥39,100,000 (Direct Cost : ¥39,100,000)
|Keywords||3D integration / Image processing system / Vision chip / High dielectric constant C / Computational sensor / Image data compression / Adaptive storage time / Motion vector / 3次元積層化 / 画像処理システム / ビジョンチップ / 高誘電率薄膜キャパシタ / コンピュテーショナルセンサ / 画像圧縮 / 適応蓄積時間 / 動きベクトル検出 / コンピュテ-ショナルセンサ / 情報圧縮センサー / 4進木構造画像センサー / シリコンウェーハ積層技術 / 微細素子のエネルギー限界 / 条件読み出し方式 / 低消費電力化 / 3次元配線|
By means of integration of an imager and parallel processing elements on a chip, we have studied on realization methods of instantaneous processing/response system of image data that is comparable to a biological vision system. The following results have been achieved.
[Visual feedback control system] For the instantaneous visual processing and control, we have designed a chip integrating photo detectors and digital general purpose processing elements. 16 x 16 pixels with processing elements has been integrated on a 5mm x 5mm chip, that operates 100MHz/600mW. A controller for the vision chip and its programming system has also implemented for successful demonstration of the visual feedback system based on the developed vision chip.
[High quality imager with data compression] For simultaneous realization of high quality imager and suppression of data bandwidth, we have successfully integrated image-processing functions into an imager. The pixel intensity variation is continuously monitore
d on the chip, so as to generate minimal output image data only for pixels that need to update. A 128 x 128 imager has been realized to demonstrate the performance. We have also realized a 64x 64 variable special resolution imager, which adaptively changes its resolution depending on target objects. It has a similarity to that of the biological retina.
[Tracking system of moving objects] For instantaneous detection of motion vectors of moving objects, we have developed a hierarchical block access imager utilizing the binary image/binary outline of objects. This sensor can access a volume of pixels at a time, so as to detect moving directions of objects comparing the successive image frames on a chip.
[Adaptive vision] For simulating the adaptability of biological vision system, we have designed a 1-D artificial silicon retina that has capabilities of spatial derivative calculation and smoothing. It has also a capability to catch edge places in real time operation.
[3D-scaled device integration] We have studied on scaled device characteristics less than 0.1um feature size requested for implementing high performance imager, accounting quantitative quantum effects. Also we have successfully developed 3-D device integration technologies by means of a wafer stacking method. It can realize 3D-integration such as imager-on-processing circuits.