| Project/Area Number |
07248105
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| Research Category |
Grant-in-Aid for Scientific Research on Priority Areas
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| Allocation Type | Single-year Grants |
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
ISHIHARA Hiroshi Tokyo Institute of Technology Frontier Collaborative Research Center Professor, フロンティア創造共同研究センター, 教授 (60016657)
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| Co-Investigator(Kenkyū-buntansha) |
YONETSU Hiroo Toyohashi University of Technology Faculty of Engineering Professor, 工学部, 教授 (90191668)
HO Kouichiro Tokyo University Faculty of Engineering Professor, 工学部, 教授 (60211538)
AMEMIYA Yoshihiro Hokkaido University Faculty of Engineering Professor, 工学部, 教授 (80250489)
SHIBATA Tadashi Tokyo University Faculty of Engineering Professor, 工学部, 教授 (00187402)
IWATA Atsushi HIROSHIMA University Faculty of Engineering Professor, 工学部, 教授 (30263734)
OKABE Youichi Tokyo University AT&T Bell Laboratories Professor (50011169)
YAMAKAWA Tsuyoshi Kyusyu Institute of Technology Faculty of Computer Science and Systems Engineering Professor (00005547)
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| Project Period (FY) |
1995 – 1998
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| Project Status |
Completed (Fiscal Year 1998)
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| Budget Amount *help |
¥162,400,000 (Direct Cost: ¥162,400,000)
Fiscal Year 1998: ¥22,200,000 (Direct Cost: ¥22,200,000)
Fiscal Year 1997: ¥44,700,000 (Direct Cost: ¥44,700,000)
Fiscal Year 1996: ¥49,000,000 (Direct Cost: ¥49,000,000)
Fiscal Year 1995: ¥46,500,000 (Direct Cost: ¥46,500,000)
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| Keywords | bio-inspired processing / nurochip / caotic circuits / imaging processor / nuron-MOS / analog-digital-merged circuits / retina chip / adaptive-learning system / 強誘電体 / パルス周波数変調 / パルス幅変調 / カオス / 神経回路 / 自己組織化 / ニューラクネットワーク / 集積回路 / シリコン / イメージセンサ / ニューロデバイス / 強誘導体 / 4端子デバイス / 適応学習 / 不揮発性メモリ |
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| Research Abstract |
In this research group, hardware implementation of multi-dimensional information which includes time domain information as well as two-dimensional special information is realized using pure-binary. multi-valued, analog and analog-digital-merged systems. Particular attention is paid in such bio-inspired system as the adaptive-learning system in which response for stimulus is changed by the past experience and the reorganizing system, and quick response based on association of ideas or rough judgement is expected.
In the research topic in which an adaptive-learning neurochip is fabricated using ferroelectric-gate FETs. a test chip was fabricated by integrating a CMOS Schmitt trigger circuit with ferroelectric-gate FETs with SrBi2Ta2O9 film on an SOI (silicon-on-insulator) structure and it was demonstrated that the output pulse frequency increased with increase of input pulse number. This operation can be regarded as an adaptive-learning function.
Concerning generation of caotic signals, two kinds of integrated circuits were fabricated ; one is the external clock typewhich is composed of capacitors and npn bipolar transistors and the other is internal clock type which is composed of astable CMOS multi-vibrators.
Concerning analog-digital-merged circuits, pulse width modulation system was imp lemented for intelligent imaging processor, in which functional image sensors, pattern matching processors, and so on are integrated in a chip. In CMOS digital and neuron MOS technologies. high-precision analog nonvolatile memories and association engine chip to look for the most resemble data were developed.
Finally, a new retina chip for edge detection was fabricated, in which the whole area except for the photo-cell area acts as the channel region of MOSFET and plays a role of two-dimensional wiring. This layout is useful in avoiding the complexity of interconnection among photo-cells.
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