Grant-in-Aid for Scientific Research (A)
|Research Institution||Osaka University|
IMAI Masaharu Osaka Univ.DEPT of CHEM.SCI.ENG., Professor, 大学院・基礎工学研究科, 教授 (50126926)
引地 信之 (株)SRA SI, ビジネス第2部・先端応用技術グループ, 課長
KIMURA Tsutomu Toyota college of Technology, Assistant, 情報工学科, 助手 (80225044)
SATO Jun Turuoka National College of Technology, Lectrer, 電気工学科, 講師 (10235351)
SHIOMI Akichika Shizuoka Univ.Faculty of Information, Lectrer, 情報学部, 講師 (60242921)
TAKEUCHI Yoshinori Osaka Univ.DEPT of CHEM.SCI.ENG., Lectre, 大学院・基礎工学研究科, 講師 (70242245)
HIKICHI Nobuyuki SRASI Corp., Business, Lab.Sec.Maneger
|Project Fiscal Year
1995 – 1997
Completed(Fiscal Year 1997)
|Budget Amount *help
¥14,000,000 (Direct Cost : ¥14,000,000)
Fiscal Year 1997 : ¥3,000,000 (Direct Cost : ¥3,000,000)
Fiscal Year 1996 : ¥3,000,000 (Direct Cost : ¥3,000,000)
Fiscal Year 1995 : ¥8,000,000 (Direct Cost : ¥8,000,000)
|Keywords||ARCHITECTURE DESIGN / ARCHITECTURE MODEL / GUI / アーキテクチャ設計教育 / アーキテクチャ・モデル / 設計支援環境|
We have performed a study on the configuration of the microprocessor design education environment and developed a prototype of the environment. Major research topics performed in this research are as follows :
(1) Architecture Information Management Method
A hardware model named FHM (Flexible Hardware Model) has been proposed, which is suitable for "reuse of design results", "design for reuse", and architecture design in the deep sub-micron technology. Then the specification of a database management system (DBMS) for FHM has been decided, and a prototype of FHM-DBMS has been developed. Finally, the prototype system has been evaluated through the design experiments using digital filters (FIR filters) and other digital signal processing module (DCT).
(2) Description and Input Methods of Architecture Information
First, architecture information has been classified so that various types of processors can be handled. Then necessary architecture parameters have been identified to describe the arc
hitecture. Next a GUI (Graphical User Interface) has been designed to input/edit/display architecture parameters between a designer and the system.
(3) Generation Method of Hardware Description
Algorithms to generate HDL (hardware description language) descriptions of processors have been developed. One of the yielded descriptions is suitable for high-speed simulation and the other is suitable for logic synthesis. Another approach to generate HDL description from "behavioral semantic description" of a processor was also investigated.
(4) Optimization Assistant Environment
Various architectural level optimization algorithms have been developed. Some of them are able to minimize execution cycles of application programs by adjusting the instruction set of the processor with consideration of (a) number of registers in CPU ; (b) amount of on-chip memories (RAM and ROM). Another algorithm is able to minimize execution cycles of VLIW (Very Long Instruction Set) type CPU core by adjusting the kinds and number of functional units.
(5) Application Program Development Environment Generation
Compiler generators and instruction set level simulator generators have been developed for scalar (pipeline) type CPU and VLIW type CPU core, respectively. These generators accept architecture parameters such as kinds and number of functional units, number of registers. Yielded compilers are to be used for performance estimation as well as object code generation for the generated CPU core. Less