HANYU Takahiro Tohoku University, Graduate School of Information Sciences, Associate Professor, 大学院・情報科学研究科, 助教授 (40192702)
XIAOWEI Deng Tohoku University, Graduate School of Information Sciences, Research Associate, 大学院・情報科学研究科, 助手 (70261576)
For next-generation super chips, not only computer-worldapplications but also real-world applications will be important targets. In the real-world applicatins, thers is data flow passing through the real world, so that the real-world environment is changed to be the desired states by control actions. The typical applications are robotics, intelligent vehicle, factory automation, real-time instrumentation and control systems, and so on. In this reaearch project high-performance VLSI processors and their key technologies based on new multiple-valued integrated circuits have been developed an follows :
(1)VLSI processors for high-speed collision detection and 3-Dimensional instrumentation
In the collision-detection operation between a vehicle and obstacles, high-computational power is essentially required in not only coordinate transformation but also matching operation between vehicle and obstacle pixels. In the proposed VLSI processor for high-speed collision detection, a content-addressa
ble memory is introduced to store vehicle pixel information, so that the matching operation is drastically accelerated. Since vehicle pixel information is predetermined and not changed, the high-performance CAM based on a ROM cell is proposed. A parallel and pipelined architecture for the high-speed coordinate transformation is also proposed based on two-dimensional vector rotations and matrix multiplications.
On the other hand, a high-performance VLSI architecture with an efficient memory access scheme is proposed for high-speed 3-D instrumentation. Since pixels in candidate blocks overlap, these pixel values are used repetitively by a 2-D array of processing elements (PEs). By using the 2-D PE array, only local communications are required since the image block is a 2-D array of pixel values. Moreover, a new memory-interleave technique is also proposed to concurrently access the frame memory.
(2)Low-Power Current-Mode Multiple-Valued Integrated Circuits
A new current-source control technique is proposed to design a low-power high-speed multiple-valued current-mode (MVCM) integrated circuit in a low supply voltage. The use of a defferential logic circuit (DLC) with a pair of dual-rail complementary inputs makes an input signal-voltage swing small, which results in a high driving capability at a lower supply voltage while having large static power dessipation. In the proposed DLC using switched current control, the static power dissipation is greatly reduced because current sources in non-active circuit blocks are switched off. In the current control, no additional transistors are required to control the current sources because a current-control circuit is already used in the threshold detector. As a typical example of arithmetic circuits, a new 1.5V-supply 54*54-bit multiplier based on a standard 0.8-um CMOS technology is also designed. Its performance is about ^<1.3> times faster than of a binary fastest multiplier under the normalized powerdissipation.
(3)High-Performance Multiple-Valued Content-Addressable Memory and Its Application
A new high-density multiple-valued content-addressable memory (CAM) is proposed for highly parallel search operations. Multiple-valued stored data correspond to the threshold voltage of a floating-gate MOS transistor, so that the cell circuit can be designed using only a single transistor. Since a single match line in a one-word circuit is used for performing a multi-input wired AND opearion, the magnitude comparison result between multi-digit data can be obtained simultaneously. As a result, a one-world magnitude comparison with n digits can be performed by just (n+1) steps in spite of a single-transistor cell circuit and single-match-line architecture, which makes the peripheral circuit of a CAM cell array small. Moreover, typical applications clearly demonstrate that theproposed non-volatile CAM is useful as a hardware accelerator for various real-world applications such as high-speed collision detection and highly parallel danger-detection rule matching.
Moreover, a new special-purpose 4-valued CAM is also proposed for high-speed cellular logic image processing. A universal literal in CAM cell is used to compare a 4-valued input value with various template patterns simultaneously. The universal-literal cell circuit with 4-valued data storage capability can be implemented by just a few floating-gate MOS transistors, since the cell function is performed by simple threshold operations together with logic-value conversion. As a result, the effective cell area in the proposed CAM array is greatly reduced in comparison with that in a corresponding binary CAM-based implementation. Less