Computer-Aided-Design for Analog-Digital Mixed Large Scaled Integration Circuits
| Project/Area Number |
07650399
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Yamaguchi University |
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Principal Investigator |
WATANABE Takahiro Yamaguchi University, Faculty of Engineering Associate Professor, 工学部, 助教授 (70230969)
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| Project Period (FY) |
1995 – 1996
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| Project Status |
Completed (Fiscal Year 1996)
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| Budget Amount *help |
¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 1996: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 1995: ¥900,000 (Direct Cost: ¥900,000)
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| Keywords | Analog / LSI / Analog-Digital Mixed / CAD / Layout / Layout Constraints / MCM / Test / アナログLSI / 大規模集積回路 |
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| Research Abstract |
(1) Analog Layout Constraints were classified into two groups, constraints explicitly specified by human designers and constraints implicitly derived from circuit design specifications. The latter must be well-defined and incorporated in a design data-base.
(2) A device-level global rouitng algorithm was proposed in order to obtain high-performance detailed routing under various layout constraints. The algorithm was also improved to increase efficiency and to meet with a larger layout problem, introducing a new layout-evaluation, function and a divide-and-conquer technique.
(3) A multi-layrs rouitng problem was disscussed for Multi-Chip Modules (MCM). An MCM technology is usually used as higher-density packaging technology, but its routing ploblems are similar to analog routing problems such that minimum wire-length, less routing-layrs or less vias used, and preventing signal interference or cross-talk noise. We improved a V4R algorithm and experimental results show that our approach is fairly good in the total routing length. We also discussed algorithm parameters to obtain an optimum routes.
(4) Commercial CAD systems were investigated and tried to design some sample circuit, a micro-proceesor and an simple application circuit. Design efficiency was compared between HDL design and conventional gate-level design. We also discussed test generation problems, and proposed an efficient testing for combinatorial circuits and a redundant fault detection for sequential circuits.
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Report
(3 results)
Research Products
(19 results)
