Grant-in-Aid for Scientific Research (C)
|Research Institution||Osaka University|
IMAI Masaharu Osaka Univ.DEPT of CHEM,SCI.ENG., Professor, 大学院・基礎工学研究科, 教授 (50126926)
SHIOMI Akichika Shizuoka Univ.Fuclity of Information, Lectrer, 情報学部, 講師 (60242921)
TAKEUCHI Yoshinori Osaka Univ.DEPT of CHEM,SCI.ENG., Lectrer, 大学院・基礎工学研究科, 講師 (70242245)
|Project Fiscal Year
1995 – 1997
Completed(Fiscal Year 1997)
|Budget Amount *help
¥2,300,000 (Direct Cost : ¥2,300,000)
Fiscal Year 1997 : ¥600,000 (Direct Cost : ¥600,000)
Fiscal Year 1996 : ¥400,000 (Direct Cost : ¥400,000)
Fiscal Year 1995 : ¥1,300,000 (Direct Cost : ¥1,300,000)
|Keywords||PIPELINE / PROCESSOR MODEL / VLIW PROCESSOR / GUI / パイプライン方式 / プロセッサ・モデル / VLIWプロセッサ / ASIP / パイプライン・アーキテクチャ / 機能分割 / 最適化設計 / PEAS-I|
Architecture optimization problems have been categorized into three types :
(a) Performance maximization problem is to minimize the number of execution cycles under the constraints of chip area and power consumption. This problem is to be solved when a high performance processor is designed, fore example.
(b) Area minimization problem is to minimize the chip area under the constraints of performance (execution cycles) and power consumption. This problem is to be solved when a hard read-time system is designed, for example.
(c) Power consumption minimization problem is to minimizes the power consumption of the chip under the constrains of performance and power consumption. This problem is to be solved when a battery driven system is to be designed, for example.
In this research, performance maximization problem and area minimization problem have been formalized as integer programming problems, then algorithms to solve these problems have been developed. All of these algorithms are based on the branch-and-bound method. Following algorithms have been developed.
(1) Performance maximization algorithm for scalar (pipeline) type processor
(2) Performance maximization algorithm for scalar (pipeline) type processor with consideration of the number of registers in CPU
(3) Performance maximization algorithm for scalar (pipeline) type processor with consideration of the amount of on-chip memories (RAM and ROM)
(4) Performance maximization algorithm for VLIW (pipeline) type processor with consideration of the amount of on-chip memories (RAM and ROM)
(5)Area minimization algorithm for scalar (pipeline) type processor
The effectiveness and efficiency of these algorithms have been investigated through various kinds of application programs including digital signal processing.
さらに、最適化の対象とするアーキテクチャのタイプを拡張し、VLIW(Very Long Instruction Word)アーキテクチャの性能最大化問題の定式化およびそのアルゴリズムの開発を行なった。