Grant-in-Aid for Scientific Research (A)
|Allocation Type||Single-year Grants|
|Research Institution||TOHOKU UNIVERSITY|
KOYANAGI Mitsumasa Department of Machine Intelligence and Systems Engineering, Graduate School of Engineering, Tohoku University Professor, 大学院・工学研究科, 教授 (60205531)
TSUKAMOTO Haruhiko Mitsubishi Heavy Industries, Ltd., Machine tool laboratory in Hiroshima Research, 広島研究所, 次長(研究職)
MIYAKAWA Nobuaki Fuji Xerox Co.Ltd., Electronic Component Technology Development Dept.Advanced Te, 電子技術研究所, 主幹研究員
HANE Kazuhiro Graduate School of Engineering, Tohoku University Professor, 大学院・工学研究科, 教授 (50164893)
ESASHI Masayoshi New Industry Creation Hatchery Center, Tohoku University Professor, 教授 (20108468)
NAKAMURA Tadao Graduate School of Information Sciences, Tohoku University Professor, 大学院・情報科学研究科, 教授 (80005454)
|Project Period (FY)
1996 – 1998
Completed(Fiscal Year 1998)
|Budget Amount *help
¥37,600,000 (Direct Cost : ¥37,600,000)
Fiscal Year 1998 : ¥1,500,000 (Direct Cost : ¥1,500,000)
Fiscal Year 1997 : ¥15,800,000 (Direct Cost : ¥15,800,000)
Fiscal Year 1996 : ¥20,300,000 (Direct Cost : ¥20,300,000)
|Keywords||Three Dimensional Integration Technology / Three Dimensional Integrated Shard Memory / High Speed parallel Computing System / Bus Bottle Neck / Parallel Monte Carlo Analysis / Device Simulation / Deca-nano device / ULSI|
This project aimed to develop a compact parallel computer system specific for the Monte-Carlo simulation. The results are summarized as follows :
1. Parallel computer system specific for the Monte-Carlo simulation. System ana1ysis of the first version parallel computer was completed on 1997. The second version has been designed since 1997. In second version, the communication bus and protocol are dramatically improved for speeding up the inter-processor communication. A new ring bus pipe line architecture is proposed and is introduced into the second version design. The data coming through the ring bus are processed at each processing unit in parallel and sent to next processing unit. Therefore, a combined system of ring bus and processing units act as a huge pipe line. The architecture level design has been completed.
2. Three dimensional integration technology
The following three key technologies have been developed for three-dimensional integrated circuit.
(a) Micro-bump formation
lift-off technology has been developed for the micro-bump formation. Indium(In)-gold(Au) micro-bumps as small as 5 mu m can be easily formed by using this technology. It was found that thin tungsten film inserted between In-Au micro-bump and aluminum electrode is very effective to reduce the contact resistance. A very low contact resistance of 0.05 OMEGA per micro-bump was obtained.
(b) Wafer alignment and bonding
Several wafers are stacked and bonded for three -dimensional integration after careful wafer alignment. A new vacuum adhesive injection method was developed for gluing the wafers. Liquid adhesive was injected into the small gap between two stacked wafers in vacuum ambient applying a mechanical pressure from both sides of wafers. Injected liquid adhesive was cured at 180ﾟC.This procesure improved the bondability of wafers and the electrical characteristics of micro-bumps.
(c) Vertical interconnection and wafer thinning
The deep trench with the diameter of 3 mu m and the depth of 60 mum has been formed on a silicon substrate after optimizing the ICP(Inductively Coupled Plasma) etching condition. After the trench etching, oxidation, poly-silicon deposition, impurity diffusion and etching back of poly-silicon by CMP were performed. Thus, a low resistive vertical interconnection for three-dimensional integrated circuit has been successfully formed. Less