|Budget Amount *help
¥2,500,000 (Direct Cost : ¥2,500,000)
Fiscal Year 1997 : ¥1,600,000 (Direct Cost : ¥1,600,000)
Fiscal Year 1996 : ¥900,000 (Direct Cost : ¥900,000)
We have developed methods for designing combined arithmetic circuits which execute consecutive addition/subtractions and multiplications appearing in degital signal processing as one operation, and also developed high-speed computing method using these circuits. The main results are as follows :
1. We have designed an add-multiply-adder which executes consecutive addition, multipli-cation and addition appearing often in degital signal processing as one operation, and shown its applications.
2. We have developed a new high-speed square rooting algorithm using a multiply-adder which executes consecutive multiplication and addition as one operation.
3. We have developed a new method for generating powers of an operand, such as recirocal, square root, reciprocal square root, reciprocal square, reciprocal cube and so on, using a multiplier with operand modifier.
4. We have developed an adder which is optimal in theory and very efficient in practice, under the assumption of left-to-righ input arrival.
5. We have developed two hardware algorithms for modular division with very large modulus which is required in cryptosystems. One is based on the extended Euclidean algorithm and the other is based on the binay GCD algorithm.
6. We have developed massively parallel algorithms for executing arithmetic operations on a functional memory and have developed a method for motion vector detection using them.