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A Research on the realization of three-level logic networks

Research Project

Project/Area Number 08680374
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionKyusyu Institute of Technology

Principal Investigator

SASAO Tsutomu  Kyusyu Institute of Technology Departoment of Computer Science and Technology, Professor, 情報工学部, 教授 (20112013)

Co-Investigator(Kenkyū-buntansha) KAJIHARA Seiji  Kyusyu Institute of Technology Department of Computer Science and Electronics, A, 情報工学部, 助教授 (80252592)
KODA Norio  Tokuyama College of Technology Department of Computer Science and Technology, Pr, 情報電子工学科, 教授 (10099864)
Project Period (FY) 1996 – 1997
Project Status Completed (Fiscal Year 1997)
Budget Amount *help
¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 1997: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 1996: ¥1,600,000 (Direct Cost: ¥1,600,000)
KeywordsAND-OR-EXOR / Three-Level Logic / Programmable logic device / EXOR Logic Synthesis / Multi-level Logic Synthesis / Logic Minimization / Complexity of logic networks / BDD / 論理関数の分解 / AND-OR-EXOR / 論理関数の複雑度 / 非冗長論理和形 / PLD
Research Abstract

(1) AND-OR-EXOR three-level networks.
We considered design methods for AND-OR-EXOR three-level networks, where single two-input EXOR gate is used for each output. The network realizes an EXOR of two sum-of-products expressions (EX-SOP), F1 F2, where F1 and F2 are sum-of-products expressions (SOPs). The problem is to minimize the total number of different products in F1 and F2.
(2)OR-AND-OR three-level networks.
We considered the number of gates to realize logic functions by OR-AND-OR three-level networks under the condition that both true and complemented variables are available, and each gate has no fan-in and fan-out constraints. We show that an arbitrary n-variable function can be realized by an OR-AND-OR three-level network with at most 2^{r+1}+1 gates、where n=2r and r are integers. We developed a heuristic algorithm to design OR-AND-OR three-level networks, and compared the number of gates for three-level networks with two-level ones.
(3) Bi-decomposition.
A logic function f has a disjoint bi-decomposition iff f can be represented as f=h(g_1(X_1), g_2(X_2)), where X_1 and X_2 are disjoint set of variables, and h is an arbitrary two-variable logic function. We showed a fast method to find bi-decompositions without using decomnposition chart. Also, we enumerated the number of functions having bi-decompositions. When the function has a bi-decomposition, three-level network is easy to derive.
(4)Generalized Reed-Muller expressions
A generalized Reed-Muller Expression (GRM) is obtained by negating some of the literals in a positive polarity Reed-Muller expression (PPRM).There are at most 2^{n{2^{n-1}} different GRMs for an n-variable function. A minimum GRM is one with the fewest products. We showed some properties and a minimization algorithm for GRMs. The minimization algorithm is based on binary decision diagrams. We also developed GRMIN2, heuristic minimization program for GRMs. We also developed an easily testable realization for GRMs.

Report

(3 results)
  • 1997 Annual Research Report   Final Research Report Summary
  • 1996 Annual Research Report
  • Research Products

    (47 results)

All Other

All Publications (47 results)

  • [Publications] D.Debnath and T.Sasao: "GRMIN2:A heuristic simplification algorithm for generalized Read-Muller expressions" IEEE Proceedings,Computers and Digital Tecniques. 143・6. 376-384 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] J.T.Butler and T.Sasao: "Average number of nodes in binary decision diagrams of Fibonacci functions" Fibonacci Quarterly. 34・5. 413-422 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao and J.T.Butler: "Planar decision diagrams for multiple-valued functions" Multiple-valued Logic:An International Journal. 1・1. 39-46 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] J.T.Butler, D.S.Herscovici, T.Sasao, and R.J.Barton: "Average and worst case number of nodes in decision diagrams of symmetric multiple-valued functions" IEEE Transactions on Computers. 46.4. 491-494 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao: "Easily testable realizations for generalized Reed-Muller expressions" IEEE Transactions on Computer. 46・6. 709-716 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: "Minimization of AND-OR-EXOR three-level networks with AND gate sharing" IEICE Trans.Information and Systems. E80-D-10. 1001-1008 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao and M.Fujita(ed.): "Representation of Descrete Functions" Kluwer Academic Publishers, 331 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao and D.Debnath: "Generalized Reed-Muller expressions : Complexty and an exact minimization algorithm, "" IEICE Transactions. Vol.E79-A,No.12. 2123-2130 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: "GRMIN2 : A heuristic simplification algorithm for generalized Reed-Muller expressions" IEE Priceedings, Computers and Digital Techniques. Vol.143.No.6. 376-384 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] J.T.Butler and T.Sasao: "Aberage number of nodes in binary decision diagrams of Fibonacci functions" Fibonacci Quarterly. Vol.34.5. 413-422 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao and J.Butler: "Planar decision diagrams for multiple-valued functions" Multiple-valued Logic : An International Journal. Vol.1, No.1. 39-46 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] J.T.Butler, D.S.Herscovici, T.Sasao and R.J.Barton: "Average and worst case number of nodes in decision diagrams of symmetric multiple-valued functions" IEEE Transactions on Computers. Vol.46, No.4. 491-494 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao: "Easily testable realizations for generalized Reed-Muller expressions."" IEEE Transactions on Computer. Vol.46, No.6. 709-716 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: "Minimization of AND-OR-EXOR three-level networks with AND gate sharing" IEICE Trans.Information and Systems. Vol.E80-D,No.10. 1001-1008 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao and J.T.Butler: "A Method to represent multiple-output switching functions by using multi-valued decision deagrams"" IEEE International Symposium on Muliple-Valued Logic, Santiago de Compostela, Spain, May 29-31. 248-254 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] J.T.Butler, J.L.Nowlin, and T.Sasao: "Planarity in ROMDD's of multiple-valued symmetric functions" IEEE International Symposium on Multiple-Valued Logic, Santiago de Compostela, Spain, May 29-31. 236-241 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: "Minimization of AND-OR-EXOR three-level networks with AND gate sharing" the Sixth Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'96), Fukuoka, Japan, Nov.25-26. 67-73 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Hafiz Md.Hasan Babu and T.Sasao: "A Method to represent multiple-output switching functions by using binary decision diagrams" the Sixth Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'96), Fukuoka, Japan, Nov.25-26. 212-217 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: " An optimization of AND-OR-EXOR three-level networks" Asia and South Pacific Design Autmation Conference 1997 (ASP-DAC'97), Makuhari, Japan, Jan.28-31. 545-550 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Y.Iguchi, T.Sasao, M.Matsuura: "On properties of Kleene TDDs" Asia and South Pacific Design Autmation Conference 1997 (ASP-DAC'97), Makuhari, Japan, Jan.28-31. 473-476 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao and J.T.Butler: "On bi-decompositions of logic functions" ACM/IEEE International Workshop on Logic Synthesis, Tahoe City, California, May 18-21. (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao: "Ternary decision deagrams : survey" (invited paper)" IEEE International Symposium on Multiple-Valued Logic, Nova Scotia, Canada, May 28-30. 241-250 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao and J.T.Butler: "Comparison of the worst and best sum-of-products expressions for multipli-valued functions" IEEE International Symposium on Multiple-Valued Logic, Nova Scotia, Canada, May 28-30. 55-60 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: "Exclusive-OR of two sum-of-products expressions : simplification and an upper bound on the number of products" Proc.3rd International Workshop on Application of the Reed-Muller Expansion in Circuit Design (Reed-Muller'97), Oxford, U.K., Sept.19-20. 45-60 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao: "Complexity measure for AND-EXOR expressions" Proc.3rd International Workshop on Applications of the Reed-Muller Expansion in Circuit Design (Reed-Muller'97), Oxfrod, U.K.Sept.19-20. 145-156 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] S.Kajihara and T.Sasao: "On adders with minium test" IEEE The 6th Asian Test Symposium, November 17-19,1997, Akita, Japan. 10-15

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Y.Iguchi, T.Sasao and M.Matsuura: "Decomposition of Kleene-TDDs" IEEE The 6th Asian Test Symposium, November 17-19,1997, Akita, Japan. 234-239

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Hafix Md.Hasan Babu and T.Sasao: "Representations of multiple-output logic functions using shared multi-terminal binary decision diagrams" the Seventh Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'97), Osaka, Japan, Nov.25-26. 25-32 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] R.Drechsler, R.S.Stankovic, and T.Sasao: "Spectral transforms and word-level decision diagrams" the Seventh Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'97), Osaka, Japan, Nov.25-26. 39-44 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] R.S.Stankovic, and T.Sasao: "Spectral Interpretation of TDDs" the Seventh Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'97), Osaka, Japan, Nov.25-26. 45-50 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] R.Stankovic and T.Sasao: "Decision diagrams for discrete functions : Classification and unified interpretation" Asia and South Pacific Design Automation Conference, ASP-DAC'98, Feb.439-446 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: "A heuristic algorithm to design AND-OR-EXOR three-level networks" Asia and South Pacific Design Automation Conference, ASP-DAC'98, Feb.69-74 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Sasao and M.Fujita (ed.): Representation of Descrete Functions. Kluwer Academic Publishers, (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: "GRMIN2:A heuristic simplification algorithm for generalized Reed-Muller expressions" IEE Proceedings,Computers and Digital Techniques. 143・6. 376-384 (1996)

    • Related Report
      1997 Annual Research Report
  • [Publications] J.T.Butler and T.Sasao: "Average number of nodes in binary decision diagrams of Fibonacci functions" Fibonacci Quarterly. 34・5. 413-422 (1996)

    • Related Report
      1997 Annual Research Report
  • [Publications] T.Sasao and J.T.Butler: "Planar decision diagrams for multiple-valued functions" Multiple-valued Logic:An International Journal. 1・1. 39-46 (1996)

    • Related Report
      1997 Annual Research Report
  • [Publications] J.T.Butler,D.S.Herscovici,T.Sasao,and R.J.Barton: "Average and worst case number of nodes in decision diagrams of symmetric multiple-valued functions" IEEE Transactions on Computers. 46・4. 491-494 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] T.Sasao: "Easily testable realizations for generalized Reed-Muller expressions" IEEE Transactions on Computer. 46・6. 709-716 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] D.Debnath and T.Sasao: "Minimization of AND-OR-EXOR three-level networks with AND gate sharing" IEICE Trans.Information and Systems. E80-D・10. 1001-1008 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] T.Sasao and M.Fujita(ed.): "Representation of Descrete Functions" Kluwer Academic Publishers, 331 (1996)

    • Related Report
      1997 Annual Research Report
  • [Publications] T.Sasao and D.Debnath: "Generalized Reed-Muller expressions : Complexity and an exact minimization algorithm" IEICE Transactions. E79-A No.12. 2123-2130 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] D.Debnath and T.Sasao: "GRMIN2: A heuristic simplification algorithm for generalized Reed-Muller expressions" IEE Proceedings,Computers and Digital Techniques. Vol.143 No.6. 376-384 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] T.Sasao and J.T.Butler: "Planar decision diagrams for multiple-valued functions" Multiple-valued Logic : An International Journal. Vol.1 No.1. 39-46 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] T.Sasao: "Easily testable realizations for generalized Reed-Muller expressions" IEEE Transactions on Computer(accepted for publication).

    • Related Report
      1996 Annual Research Report
  • [Publications] J.T.Butler,D.S.Herscovici,T.Sasao and R.J.Barton: "Average and worst case number of nodes in decision diagrams of symmetric multiple-valued functions" IEEE Transactions on Computer(accepted for publication).

    • Related Report
      1996 Annual Research Report
  • [Publications] J.T.Butler and T.Sasao: "Average number of nodes in binary decision diagrams of Fibonacci functions" Fibonacci Quarterly(accepted for publication).

    • Related Report
      1996 Annual Research Report
  • [Publications] T.Sasao and M.Fujita (ed.): "Representation of Discrete Functions" Kluwer Academic Publishers, 325 (1996)

    • Related Report
      1996 Annual Research Report

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Published: 1996-04-01   Modified: 2016-04-21  

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