Project/Area Number  08680374 
Research Category 
GrantinAid for Scientific Research (C)

Section  一般 
Research Field 
計算機科学

Research Institution  Kyusyu Institute of Technology 
Principal Investigator 
SASAO Tsutomu Kyusyu Institute of Technology Departoment of Computer Science and Technology, Professor, 情報工学部, 教授 (20112013)

CoInvestigator(Kenkyūbuntansha) 
KAJIHARA Seiji Kyusyu Institute of Technology Department of Computer Science and Electronics, A, 情報工学部, 助教授 (80252592)
KODA Norio Tokuyama College of Technology Department of Computer Science and Technology, Pr, 情報電子工学科, 教授 (10099864)

Project Fiscal Year 
1996 – 1997

Project Status 
Completed(Fiscal Year 1997)

Budget Amount *help 
¥2,400,000 (Direct Cost : ¥2,400,000)
Fiscal Year 1997 : ¥800,000 (Direct Cost : ¥800,000)
Fiscal Year 1996 : ¥1,600,000 (Direct Cost : ¥1,600,000)

Keywords  ANDOREXOR / ThreeLevel Logic / Programmable logic device / EXOR Logic Synthesis / Multilevel Logic Synthesis / Logic Minimization / Complexity of logic networks / 論理設計 / 論理合成 / 関数分解 / 多段論理回路 / EXOR / 検査容易化設計 / FPGA / BDD / 論理関数の分解 / 論理関数の複雑度 / 非冗長論理和形 / PLD 
Research Abstract 
(1) ANDOREXOR threelevel networks. We considered design methods for ANDOREXOR threelevel networks, where single twoinput EXOR gate is used for each output. The network realizes an EXOR of two sumofproducts expressions (EXSOP), F1 F2, where F1 and F2 are sumofproducts expressions (SOPs). The problem is to minimize the total number of different products in F1 and F2. (2)ORANDOR threelevel networks. We considered the number of gates to realize logic functions by ORANDOR threelevel networks under the condition that both true and complemented variables are available, and each gate has no fanin and fanout constraints. We show that an arbitrary nvariable function can be realized by an ORANDOR threelevel network with at most 2^{r+1}+1 gates、where n=2r and r are integers. We developed a heuristic algorithm to design ORANDOR threelevel networks, and compared the number of gates for threelevel networks with twolevel ones. (3) Bidecomposition. A logic function f has a disjoint bidecomposition iff f can be represented as f=h(g_1(X_1), g_2(X_2)), where X_1 and X_2 are disjoint set of variables, and h is an arbitrary twovariable logic function. We showed a fast method to find bidecompositions without using decomnposition chart. Also, we enumerated the number of functions having bidecompositions. When the function has a bidecomposition, threelevel network is easy to derive. (4)Generalized ReedMuller expressions A generalized ReedMuller Expression (GRM) is obtained by negating some of the literals in a positive polarity ReedMuller expression (PPRM).There are at most 2^{n{2^{n1}} different GRMs for an nvariable function. A minimum GRM is one with the fewest products. We showed some properties and a minimization algorithm for GRMs. The minimization algorithm is based on binary decision diagrams. We also developed GRMIN2, heuristic minimization program for GRMs. We also developed an easily testable realization for GRMs.
