| Project/Area Number | 08680374 |
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Kyusyu Institute of Technology |
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Principal Investigator |
SASAO Tsutomu Kyusyu Institute of Technology Departoment of Computer Science and Technology, Professor, 情報工学部, 教授 (20112013)
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| Co-Investigator(Kenkyū-buntansha) |
KAJIHARA Seiji Kyusyu Institute of Technology Department of Computer Science and Electronics, A, 情報工学部, 助教授 (80252592)
KODA Norio Tokuyama College of Technology Department of Computer Science and Technology, Pr, 情報電子工学科, 教授 (10099864)
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| Project Period (FY) |
1996 – 1997
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| Project Status |
Completed(Fiscal Year 1997)
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| Budget Amount *help |
¥2,400,000 (Direct Cost : ¥2,400,000)
Fiscal Year 1997 : ¥800,000 (Direct Cost : ¥800,000)
Fiscal Year 1996 : ¥1,600,000 (Direct Cost : ¥1,600,000)
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| Keywords | AND-OR-EXOR / Three-Level Logic / Programmable logic device / EXOR Logic Synthesis / Multi-level Logic Synthesis / Logic Minimization / Complexity of logic networks / BDD / 論理関数の分解 / AND-OR-EXOR / 論理関数の複雑度 / 非冗長論理和形 / PLD |
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| Research Abstract |
(1) AND-OR-EXOR three-level networks.
We considered design methods for AND-OR-EXOR three-level networks, where single two-input EXOR gate is used for each output. The network realizes an EXOR of two sum-of-products expressions (EX-SOP), F1 F2, where F1 and F2 are sum-of-products expressions (SOPs). The problem is to minimize the total number of different products in F1 and F2.
(2)OR-AND-OR three-level networks.
We considered the number of gates to realize logic functions by OR-AND-OR three-level networks under the condition that both true and complemented variables are available, and each gate has no fan-in and fan-out constraints. We show that an arbitrary n-variable function can be realized by an OR-AND-OR three-level network with at most 2^{r+1}+1 gates、where n=2r and r are integers. We developed a heuristic algorithm to design OR-AND-OR three-level networks, and compared the number of gates for three-level networks with two-level ones.
(3) Bi-decomposition.
A logic function f has a disjoint bi-decomposition iff f can be represented as f=h(g_1(X_1), g_2(X_2)), where X_1 and X_2 are disjoint set of variables, and h is an arbitrary two-variable logic function. We showed a fast method to find bi-decompositions without using decomnposition chart. Also, we enumerated the number of functions having bi-decompositions. When the function has a bi-decomposition, three-level network is easy to derive.
(4)Generalized Reed-Muller expressions
A generalized Reed-Muller Expression (GRM) is obtained by negating some of the literals in a positive polarity Reed-Muller expression (PPRM).There are at most 2^{n{2^{n-1}} different GRMs for an n-variable function. A minimum GRM is one with the fewest products. We showed some properties and a minimization algorithm for GRMs. The minimization algorithm is based on binary decision diagrams. We also developed GRMIN2, heuristic minimization program for GRMs. We also developed an easily testable realization for GRMs.
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